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Design of a Messageflow Processor with Chip-based Inter-processors Communication Function

Design of a Messageflow Processor with Chip-based Inter-processors Communication Function
一种具有芯片间通信功能的消息流处理器设计
批准号:
09558031
负责人:
SHIBAYAMA Kiyoshi
金额:
$7.3万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1997
资助国家:
日本
项目状态:
已结题
起止时间:
1997 至 1999

项目摘要

项目成果

SHIBAYAMA Kiyoshi的其他基金

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相关文献

中文摘要
翻译
主动消息(AM)是一种有效的分布式并行计算机消息传递通信方案。AM是最好的消息传递通信方案之一,因此AM已经在多台并行计算机上实现,以实现显着的性能改善。AM的新特点是在处理器间的通信消息中指定接收处理器应该如何处理该消息,在本研究中,我们提出了一种新的通信方案,提高了AM的性能和可用性。我们称我们的方案为“主动线程消息(AT-消息)”。AT-Message是通过使用两个线程来实现的,这两个线程是在每个处理器上执行的独立控制流。一个线程用于计算,另一个线程用于处理接收到的消息。这两个线程并行执行以实现低开销通信。此外,在设计AT-Message时,我们研究了软件(如用户程序和操作系统)和硬件(如处理器和网络控制器)之间的最佳折衷点,成功地实现了AT-Message用户级通信的安全性和高性能。通过使用AT-Message,我们可以构建一个更高的性能和更容易编程的大规模并行计算机的情况下,使用原始AM。在这项研究中,我们还提出了一个详细的设计,有效地实现AT-Message的基本处理器体系结构。
英文摘要
"Active Messages (AM) " has been proposed as an efficient message passing communication scheme for distributed memory parallel computers. AM is one of the best message passing communication schemes, and therefore AM has been implemented on several parallel computers to achieve the dramatic performance improvements. The novel feature of AM is that, in an inter-processor communication message, it is specified how the receiving processor should handle the message.In this research, we present a new communication scheme which improves AM in both the performance and availability. We call our scheme "Active Threaded Message (AT-Message) ". AT-Message is implemented by using two threads, which are independent control flows executed on each processor. One thread is for calculation, and the other for handling of received messages. These two threads are executed in parallel to achieve the low overhead communication. Furthermore, on designing AT-Message, we had investigated the optimal trade-off point between the software (such as a user program and an OS) and the hardware (such as a processor and a network controller), and we could succeed to realize both of safety and high-performance in the user-level communication of AT-Message. By employing AT-Message, we can construct an higher-performance and more easily-programmable massively parallel computer than the case employing original AM.In this research, we also present a detailed design of the elementary processor architecture implementing AT-Message efficiently.
期刊论文(25)
专著(0)
科研奖励(0)
会议论文
Hiroaki HIRATA: "Performance Comparisons of Instruction Cache Configurations and Instruction Fetch Schemes for a Multithreaded Processor or a 1-Chip Multiprocessor"Trans. IEICE. J81-D-I-5. 718-727 (1998)
Hiroaki HIRATA:“多线程处理器或单芯片多处理器的指令高速缓存配置和指令获取方案的性能比较”Trans。
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Keizo NONAKA: "To Speed-up Gravitational N-body Problem Solving by Parallel Processing"IPSJ-SIG Notes. HPC-65-8. 39-44 (1997)
Keizo NONAKA:“通过并行处理加速引力 N 体问题解决”IPSJ-SIG 注释。
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平田 博章: "マルチスレッドプロセッサおよび1チップマルチプロセッサのための命令キャッシュ構成・命令フェッチ方式の性能評価"電子情報通信学会・論文誌. J81-D-I,5. 718-727 (1998)
Hiroaki Hirata:“多线程处理器和单芯片多处理器的指令高速缓存配置和指令获取方法的性能评估”IEICE J81-D-I,5. 718-727 (1998)。
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布目 淳: "時間的負荷変化量を考慮した超並列計算機向き動的負荷分散方式"電子情報通信学会・技術研究報告. CPSY-98-70. 73-80 (1998)
Jun Nunome:“考虑时间负载变化的大规模并行计算机的动态负载平衡方法”CPSY-98-70(1998)。
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24
    A Research on the On-the-Fly Parallelization by a Dynamic Scalar Expansion
    • 批准号:
      22500046
    • 项目类别:
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    • 资助金额:
      $2.25万
    • 财政年份:
      2010
    • 负责人:
      SHIBAYAMA Kiyoshi
    • 依托单位:
    Study on High Performance Execution Scheme for Non-Numerical Computation Programs
    • 批准号:
      13680413
    • 项目类别:
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    • 资助金额:
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    • 财政年份:
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    • 负责人:
      SHIBAYAMA Kiyoshi
    • 依托单位:
    A Research on Hierarchical Processor Architecture
    • 批准号:
      10480062
    • 项目类别:
      Grant-in-Aid for Scientific Research (B).
    • 资助金额:
      $5.89万
    • 财政年份:
      1998
    • 负责人:
      SHIBAYAMA Kiyoshi
    • 依托单位:
    A Research on a Virtual Model-Architecture for Massively Parallel Computer Systems
    • 批准号:
      08458069
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
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    • 财政年份:
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    • 负责人:
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    • 依托单位:
    海外基金