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Design of a Processor Core for Massively Parallel Computers

大规模并行计算机处理器核心的设计

基本信息

批准号：
07558156
负责人：
SHIBAYAMA Kiyoshi
金额：
$ 1.98万
依托单位：
Kyoto Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
1995
资助国家：
日本
起止时间：
1995 至 1996
项目状态：
已结题

项目摘要

Last fiscal year, we studied on the architectural design of our processor-core. Through this fiscal year, we have developed a massively parallel computer architecture which uses our processor-cores as key parts, while designing the processor-core for the implementation. In the development of a massively parallel computer, we verified the capability of the message-driven thread execution feature in our processor-core architecture to support dynamic load balancing schemes in massively parallel computers. By coupling the object-oriented paradigm with our hierarchical thread scheduling mechanism, we could succeed to balance the loads of processors in a massively parallel computer. We also proposed a novel interprocessor network architecture for massively parallel computers, and revealed its effectiveness through empirical evaluations.In parallel with the development of the massively parallel computer architecture, we have refined the processor-core architecture. By simplifying and integrating carefully the functions essential to the processor-core, we could optimize the design of the processor-core. For example, we could dramatically eliminate the overhead which would arise if the processor-core would be composed as the combination of independent units implementing theis own functions.We have designed the processor-core for the implementation using FPGA's. In the logic design phase of the processor-core, we used a hardware description language to describe the functions and behaviors of the processor-core, and verified the correctness of our design through logic simulations.

上个财政年度，我们研究了处理器核心的架构设计。在本财政年度，我们开发了一个大规模并行计算机架构，该架构使用我们的处理器内核作为关键部件，同时设计了用于实施的处理器内核。在大规模并行计算机的开发中，我们验证了我们的处理器核心架构中的消息驱动线程执行功能的能力，以支持大规模并行计算机中的动态负载平衡方案。通过将面向对象的方法与层次化的线程调度机制相结合，我们成功地解决了大规模并行计算机中处理器的负载均衡问题。我们还提出了一种新的大规模并行计算机的处理器间网络体系结构，并通过实证评估揭示了其有效性。在大规模并行计算机体系结构的发展，我们已经完善了处理器核心体系结构。通过对处理器核心的基本功能进行简化和仔细集成，我们可以优化处理器核心的设计。例如，如果处理器核心是由实现各自功能的独立单元组合而成的，我们可以大大减少开销。我们设计了使用FPGA实现的处理器核心。在处理器核的逻辑设计阶段，我们使用硬件描述语言描述了处理器核的功能和行为，并通过逻辑仿真验证了设计的正确性。