Design of a Processor Core for Massively Parallel Computers

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Last fiscal year, we studied on the architectural design of our processor-core. Through this fiscal year, we have developed a massively parallel computer architecture which uses our processor-cores as key parts, while designing the processor-core for the implementation. In the development of a massively parallel computer, we verified the capability of the message-driven thread execution feature in our processor-core architecture to support dynamic load balancing schemes in massively parallel computers. By coupling the object-oriented paradigm with our hierarchical thread scheduling mechanism, we could succeed to balance the loads of processors in a massively parallel computer. We also proposed a novel interprocessor network architecture for massively parallel computers, and revealed its effectiveness through empirical evaluations.In parallel with the development of the massively parallel computer architecture, we have refined the processor-core architecture. By simplifying and integrating carefully the functions essential to the processor-core, we could optimize the design of the processor-core. For example, we could dramatically eliminate the overhead which would arise if the processor-core would be composed as the combination of independent units implementing theis own functions.We have designed the processor-core for the implementation using FPGA's. In the logic design phase of the processor-core, we used a hardware description language to describe the functions and behaviors of the processor-core, and verified the correctness of our design through logic simulations.