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Continuous Atomic-Layer Deposition of Metal Gate/High-k Metal Oxide Gate Dielectric Stack Structure

金属栅极/高k金属氧化物栅极电介质堆叠结构的连续原子层沉积

基本信息

批准号：
13450129
负责人：
NAKAJIMA Anri
金额：
$ 7.17万
依托单位：
Hiroshima University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2003
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-13450129/
关键词：
metal gate high-k metal oxide gate dielectrics stack structure atomic-layer deposition continuous deposition zirconia hafnia 原始層成長

项目摘要

Till 2001 fiscal year, atomic-layer deposition (ALD) of ZiO_2 for the next generation gate dielectrics has been studied using (ZTB:Zr(t-OC_4H_9)_4) and H_2O. Also, an ultrathin Si nitride layer as a barrier layer for the interfacial layer was deposited on a Si substrate by ALD. Then, ALD ZiO_2 was deposited on the ALD Si nitride, forming the stack gate structure. The ALD Si-nitride layer successfully suppressed the formation of an SiO_2 interfacial layer. In 2003 fiscal year, more detail study of the growth was carried out to examine the film quality and ALD mechanism. Leak current characteristics were examined for capacitors and the current was found to be due to direct tunneling both for ALDZrO_2/ALD Si-nitride stack gate dielectrics and ALDZrO_2 gate dielectrics. Also, to suppress interface reaction between poly-Si gate and gate dielectrics, the possibility of Si nitride formation using ALD on ZrO_2 was examined. On the other hand, the possibility of HfO_2 was examined using the alternate exposure of Hf(HFAcAc)_4 and H_2O because HfO_2 is the most promising candidate for the future high-k gate dielectrics. However, films with good quality could not be obtained. n-MOSFETs with ALD Si-nitride gate dielectrics (EOT=2.3 nm) were fabricated to evaluate the thin film property for the application to the ALD high-k dielectric/ALD Si-nitride stack gate dielectrics. The maximum value of electron mobility for the ALD Si nitride is about 80% compared with that for SiO_2. However, hot-carrier induced and direct tunneling injection induced mobility degradation in transistors is smaller for the ALD Si nitride than for SiO_2. This is considered to be due to the smaller interface and bulk trap generation for the ALD Si nitride than for SiO_2. Therefore, the ALD Si-nitride gate dielectrics has a possibility to be used for 65 nm technology node generation (EOT= 1.0 nm).

到2001财政年度为止，我们已经研究了用（ZTB：Zr（t-OC_4 H_9）_4）和H_2O原子层淀积（ALD）下一代栅外延材料ZiO_2。此外，通过ALD在Si衬底上沉积作为界面层的阻挡层的Si 3 N4 Si氮化物层。然后，在ALD氮化硅上沉积ALD氧化硅，形成叠层栅结构。ALD氮化硅层成功地抑制了SiO_2界面层的形成。在2003财政年度，进行了更详细的研究，以检查薄膜质量和ALD机制的增长。研究了电容器的漏电流特性，发现ALDZrO_2/ALD氮化硅叠层栅漏电流和ALDZrO_2栅漏电流都是由直接隧穿引起的。此外，为了抑制多晶硅栅极和栅极电介质之间的界面反应，研究了使用ALD在ZrO_2上形成Si氮化物的可能性。另一方面，我们利用Hf（HFAcAc）_4和H_2O的交替曝光来验证HfO_2的可能性，因为HfO_2是未来高k栅漏的最有希望的候选材料。然而，不能获得具有良好质量的膜。制造了具有ALD氮化硅栅极外延层（EOT=2.3 nm）的n-MOSFET，以评估应用于ALD高k电介质/ALD氮化硅叠层栅极外延层的薄膜特性。ALD氮化硅的电子迁移率最大值约为SiO_2的80%。然而，热载流子引起的和直接隧穿注入引起的晶体管中的迁移率退化对于ALD Si氮化物比对于SiO_2小。这被认为是由于ALD Si氮化物比SiO_2产生更小的界面和体陷阱。因此，ALD氮化硅栅极外延层有可能用于65 nm技术节点生成（EOT= 1.0 nm）。

项目成果

期刊论文数量（107）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Anri Nakajima: "Atonic-Layer-Deposited Ultrathin Si-Nitride Gate Dielectrics -A Better Choice for Sub-tunneling Gate Dielectrics-"Technical Digest of the 2003 IEEE International Electron Devices Meeting. 657-660 (2003)

Anri Nakajima：“Atonic-Layer-Deposited Ultrathin Si-Nitride Gate Dielectrics -A Better Choice for Sub-tunneling Gate Dielectrics -”2003 年 IEEE 国际电子器件会议技术文摘。