Continuous Atomic-Layer Deposition of Metal Gate/High-k Metal Oxide Gate Dielectric Stack Structure

到2001年，利用（ZTB:Zr(t-OC_4H_9)_4）和H_2O对下一代栅极电介质ZiO_2的原子层沉积（ALD）进行了研究。此外，在硅衬底上沉积了超薄氮化硅层作为界面层的阻挡层。然后在氮化硅表面沉积ALD ZiO_2，形成叠层栅结构。ALD硅氮化层成功抑制了SiO_2界面层的形成。在2003财政年度，对生长进行了更详细的研究，以检验薄膜质量和ALD机制。对电容器的漏电流特性进行了测试，发现漏电流是由ALDZrO_2/ALD硅氮化物堆叠栅介质和ALDZrO_2栅介质的直接隧穿引起的。同时，为了抑制多晶硅栅极和栅极介质之间的界面反应，研究了在ZrO_2上ALD生成氮化硅的可能性。另一方面，通过Hf(HFAcAc)_4和H_2O的交替暴露来考察HfO_2的可能性，因为HfO_2是未来高k栅极介电材料最有希望的候选材料。然而，无法获得高质量的影片。制备了具有ALD硅氮化栅极介电体（EOT=2.3 nm）的n- mosfet，以评估其薄膜性能，并将其应用于ALD高k介电体/ALD硅氮化栅极介电体。ALD氮化硅的电子迁移率最大值约为SiO_2的80%。然而，热载流子诱导和直接隧道注入诱导的晶体管迁移率下降对于ALD氮化硅比SiO_2要小。这被认为是由于ALD氮化硅比SiO_2产生更小的界面和大块陷阱。因此，ALD硅氮化栅极电介质有可能用于65 nm技术的节点生成（EOT= 1.0 nm）。

Till 2001 fiscal year, atomic-layer deposition (ALD) of ZiO_2 for the next generation gate dielectrics has been studied using (ZTB:Zr(t-OC_4H_9)_4) and H_2O. Also, an ultrathin Si nitride layer as a barrier layer for the interfacial layer was deposited on a Si substrate by ALD. Then, ALD ZiO_2 was deposited on the ALD Si nitride, forming the stack gate structure. The ALD Si-nitride layer successfully suppressed the formation of an SiO_2 interfacial layer. In 2003 fiscal year, more detail study of the growth was carried out to examine the film quality and ALD mechanism. Leak current characteristics were examined for capacitors and the current was found to be due to direct tunneling both for ALDZrO_2/ALD Si-nitride stack gate dielectrics and ALDZrO_2 gate dielectrics. Also, to suppress interface reaction between poly-Si gate and gate dielectrics, the possibility of Si nitride formation using ALD on ZrO_2 was examined. On the other hand, the possibility of HfO_2 was examined using the alternate exposure of Hf(HFAcAc)_4 and H_2O because HfO_2 is the most promising candidate for the future high-k gate dielectrics. However, films with good quality could not be obtained. n-MOSFETs with ALD Si-nitride gate dielectrics (EOT=2.3 nm) were fabricated to evaluate the thin film property for the application to the ALD high-k dielectric/ALD Si-nitride stack gate dielectrics. The maximum value of electron mobility for the ALD Si nitride is about 80% compared with that for SiO_2. However, hot-carrier induced and direct tunneling injection induced mobility degradation in transistors is smaller for the ALD Si nitride than for SiO_2. This is considered to be due to the smaller interface and bulk trap generation for the ALD Si nitride than for SiO_2. Therefore, the ALD Si-nitride gate dielectrics has a possibility to be used for 65 nm technology node generation (EOT= 1.0 nm).