权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Flash memory having a few numbers of floating nanometer-scale dot and atomic-layer-deposited tunnel gate dielectrics

具有少量浮动纳米级点和原子层沉积隧道栅极电介质的闪存

基本信息

批准号：
16360176
负责人：
NAKAJIMA Anri
金额：
$ 6.85万
依托单位：
Hiroshima University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2004
资助国家：
日本
起止时间：
2004 至 2005
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-16360176/
关键词：
Floating gate Nano dot Flash memory Free energy Soliton Single electron effect Si Few number of dot 原子層成長トンネルゲート絶縁膜

项目摘要

For scaling of flash memory, the device having a few numbers of floating nanometer-scale dot has been proposed. The purpose of this study is to fabricate the flash memory having a few numbers of floating nanometer-scale dot with precise control of the number, position, and size by using electron beam (EB) lithography, and examine the channel conduction mechanism of carrier and retention mechanism, for clarify the scaling limit of the device. Also, another purpose is to use atomic-layer-deposited tunnel gate dielectrics for the improvement of retention time and right/erase time.For the purpose, we fabricated a few number of floating dot on the Si narrow channel or Si plane channel by using the EB lithography and dry and wet etchings, and investigated the electrical characteristics with systematically changing the number, size of the dot and the distance between the adjacent dots. By comparing the electrical characteristics of the device with and without the floating dots, we confirmed that the device with floating dots indeed realizes a memory operation at room temperature. By estimating the amount of the hysteresis of the device as a function of the dot number, we found that the amount of the hysteresis increases with the dot number along the channel. However, the hysteresis has no correlation with the number of the dot along the width of the channel. If the dot number is large, the retention time will not be shorten even when some of the dots have a leakage. Therefore, taking the retention time into account, increasing the dot number along the channel is important for improving the memory characteristics.As to the usage of atomic-layer-deposited tunnel gate dielectrics for the improvement of retention time and right/erase time, we could not carried out. Therefore, we will do this in future.

对于闪存的缩放，已经提出了具有几个浮动纳米级点的器件。本研究的目的是利用电子束微影技术制作具有少量纳米级浮动点的快闪记忆体，并精确控制其数量、位置与大小，并探讨其载子沟道传导机制与保持机制，以厘清元件的尺寸限制。同时，利用原子层淀积的隧道栅结构，在硅窄沟道和硅平面沟道上，采用电子束光刻和干、湿刻蚀的方法制作了少量的浮点，并通过系统地改变浮点的数量、大小和间距，研究了浮点的电学特性。通过比较有无浮点的器件的电学特性，我们证实了有浮点的器件确实实现了室温下的存储操作。通过估计器件的滞后量作为点数目的函数，我们发现滞后量随着沿通道的点数目沿着增加。然而，滞后与沿沟道宽度沿着的点的数量没有相关性。如果点的数量很大，即使当一些点有泄漏时，保留时间也不会缩短。因此，考虑到保持时间，增加沿着沟道的点数对于改善存储器特性是重要的。至于使用原子层沉积的隧道栅来改善保持时间和正确/擦除时间，我们无法实现。因此，我们将来会这样做。