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Flash memory having a few numbers of floating nanometer-scale dot and atomic-layer-deposited tunnel gate dielectrics

Flash memory having a few numbers of floating nanometer-scale dot and atomic-layer-deposited tunnel gate dielectrics
具有少量浮动纳米级点和原子层沉积隧道栅极电介质的闪存
批准号:
16360176
负责人:
NAKAJIMA Anri
金额:
$6.85万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
2004
资助国家:
日本
项目状态:
已结题
起止时间:
2004 至 2005

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中文摘要
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英文摘要
For scaling of flash memory, the device having a few numbers of floating nanometer-scale dot has been proposed. The purpose of this study is to fabricate the flash memory having a few numbers of floating nanometer-scale dot with precise control of the number, position, and size by using electron beam (EB) lithography, and examine the channel conduction mechanism of carrier and retention mechanism, for clarify the scaling limit of the device. Also, another purpose is to use atomic-layer-deposited tunnel gate dielectrics for the improvement of retention time and right/erase time.For the purpose, we fabricated a few number of floating dot on the Si narrow channel or Si plane channel by using the EB lithography and dry and wet etchings, and investigated the electrical characteristics with systematically changing the number, size of the dot and the distance between the adjacent dots. By comparing the electrical characteristics of the device with and without the floating dots, we confirmed that the device with floating dots indeed realizes a memory operation at room temperature. By estimating the amount of the hysteresis of the device as a function of the dot number, we found that the amount of the hysteresis increases with the dot number along the channel. However, the hysteresis has no correlation with the number of the dot along the width of the channel. If the dot number is large, the retention time will not be shorten even when some of the dots have a leakage. Therefore, taking the retention time into account, increasing the dot number along the channel is important for improving the memory characteristics.As to the usage of atomic-layer-deposited tunnel gate dielectrics for the improvement of retention time and right/erase time, we could not carried out. Therefore, we will do this in future.
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会议论文
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使用重掺杂硅单电子晶体管的 XOR 电路的室温操作
DOI: --
发表时间: 2006
期刊: 信学技報 IEICE Technical Report ED2005・227
影响因子: --
作者: [田中憲光, 高橋応明, 伊藤公一, 山本伸一, 三浦 周, 他, 大倉 健作, 大倉 健作]
通讯作者: 大倉 健作
DOI: --
发表时间: 2006
期刊: 信学技報 IEICE Technical Report ED2005・225
影响因子: --
作者: [田中憲光, 高橋応明, 伊藤公一, 山本伸一, 三浦 周, 他, 大倉 健作]
通讯作者: 大倉 健作
DOI: 10.1063/1.1894594
发表时间: 2004-09
期刊: Applied Physics Letters
影响因子: 4
作者: [T. Kitade;K. Ohkura;A. Nakajima]
通讯作者: T. Kitade;K. Ohkura;A. Nakajima
DOI: 10.1063/1.2143116
发表时间: 2005-12
期刊: Journal of Applied Physics
影响因子: 3.2
作者: [K. Ohkura;T. Kitade;A. Nakajima]
通讯作者: K. Ohkura;T. Kitade;A. Nakajima
Study of flashmemory using organic and molecular materials
  • 批准号:
    21360012
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
  • 资助金额:
    $12.23万
  • 财政年份:
    2009
  • 负责人:
    NAKAJIMA Anri
  • 依托单位:
Research of reliable Ge transistor having atomic layer deposited gate dielectrics
  • 批准号:
    19360164
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
  • 资助金额:
    $11.98万
  • 财政年份:
    2007
  • 负责人:
    NAKAJIMA Anri
  • 依托单位:
Continuous Atomic-Layer Deposition of Metal Gate/High-k Metal Oxide Gate Dielectric Stack Structure
  • 批准号:
    13450129
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
  • 资助金额:
    $7.17万
  • 财政年份:
    2001
  • 负责人:
    NAKAJIMA Anri
  • 依托单位:
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