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An Electroplating of Low Resistivity Copper Interconnection Lines

低电阻率铜互连线的电镀

基本信息

批准号：
15560281
负责人：
HARA Tohru
金额：
$ 2.24万
依托单位：
Hosei University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2004
项目状态：
已结题

项目摘要

Propagation delay time in advanced logic LSI's is determined mainly by the CR time constant in the multi-level interconnection. Therefore, reduction of interconnection resistance with employing Cu layer is the most important factor to manufacture high speed LSI's. Although resistivity increases markedly with decreasing line width in the Cu interconnection layers, specifically at widths below 100 nm, little works have been done for the reduction of resistivity. Quantitative measurement of resistivity is also difficult in this interconnection layer. This work indicates clearly that resistance of 60 nm wide Cu Damascene line is determined by that of 16 nm thick nucleated Cu layer.Resistivity is 3 μΩ-cm in 300 nm thick Cu layers. It increases rapidly with decreasing thickness and reaches 12 μΩ-cm at thickness of 50 nm. This increase is due to the reduction of grain size and (200) orientation, increasing of stress and also to the inhomogeneous nucleation. It has been found that resistivity … More of 16 nm thick nucleated layer is important in the manufacturing of 60 nm wide Cu Damascene interconnection lines. Low resistivity 16 nm thick Cu interconnection layer can be electroplated when the nucleation on the seed layer can be achieved uniformly. Uniform nucleation has practically been studied with employing newly developed electrolytic solution of copper-hexafluoro-silicate. This improvement can also be attained by the surface cleaning of Cu seed layer, optimization of additive contamination, deposition and formation of low stress seed layer and also by the deposition of low stress barrier layer instead of conventional barrier layer of TaN. Relation of these process parameters with the resistivity of thin Cu layer has been studied quantitatively in this work.As a result of these fundamental research works, resistivity of 50 nm thick Cu layer decreases from 12 μΩ-cm in conventional layer to 3 μΩ-cm in this layer developed by us. These processes are very useful for the electroplating of low resistivity 16 nm thick Cu layers. Three time higher speeds can be attained when this Cu Damascene interconnection line is used. Less

在高级逻辑LSI中，传播延迟时间主要由多电平互连中的CR时间常数决定。因此，降低互连电阻是制造高速大规模集成电路的最重要的因素，虽然铜互连层的电阻率随着线宽的减小而显著增加，特别是在100 nm以下的线宽，但在降低电阻率方面所做的工作很少。在这种互连层中，电阻率的定量测量也是困难的。研究表明，60 nm宽的大马士革铜线的电阻是由16 nm厚的形核铜层决定的，在3 0 nm厚的铜层中的电阻为3μΩ-cm。随着厚度的减小，薄膜厚度迅速增大，在50 nm处达到12μΩ-cm。这是由于晶粒度和(200)晶面的减小、应力的增大以及形核的不均匀所致。已经发现，电阻率…在制造60 nm宽的大马士革铜互连线时，更多的16 nm厚的成核层是重要的。当种子层上的形核均匀时，可以电镀出16 nm厚的低电阻率铜互连层。用新研制的六氟硅酸铜电解液对均匀成核进行了实际研究。这一改善还可以通过清理铜种子层表面，优化添加剂污染，沉积和形成低应力种子层，以及通过沉积低应力阻挡层来代替传统的TaN阻挡层来实现。定量地研究了这些工艺参数与薄铜层电阻率的关系，使50 nm厚的铜层的电阻率从常规铜层的12μΩ-cm降到了我们研制的50 nm厚铜层的3μΩ-cm。这些工艺对低电阻率16 nm厚铜层的电镀是非常有用的。使用这条铜大马士革互连线，速度可以提高三倍。较少