An Electroplating of Low Resistivity Copper Interconnection Lines

在先进逻辑大规模集成电路中，传播延迟时间主要由多层互连中的CR时间常数决定。因此，采用铜层降低互连电阻是制造高速LSI的最重要因素。虽然电阻率随着Cu互连层中线宽的减小而显著增加，特别是在低于100 nm的宽度处，但是对于电阻率的减小几乎没有进行任何工作。在该互连层中，电阻率的定量测量也是困难的。结果表明，60 nm宽的Cu镶嵌线的电阻由16 nm厚的Cu成核层的电阻决定，300 nm厚的Cu成核层的电阻率为3 μΩ·cm。随着厚度的减小，它迅速增加，在50 nm厚度时达到12 μΩ-cm。这种增加是由于晶粒尺寸和（200）取向的减小，应力的增加以及不均匀形核。已经发现电阻率 ...更多信息 16 nm厚的成核层在60 nm宽的Cu大马士革互连线的制造中是重要的。当晶种层上的成核均匀时，可以电镀低电阻率的16 nm厚的Cu互连层。采用新研制的六氟硅酸铜电解液进行了均匀形核的实际研究。这种改进也可以通过Cu籽晶层的表面清洁、添加剂污染的优化、低应力籽晶层的沉积和形成以及还可以通过沉积低应力阻挡层代替传统的TaN阻挡层来实现。定量地研究了这些工艺参数与薄Cu层电阻率的关系，通过这些基础性的研究工作，使50 nm厚Cu层的电阻率从常规层的12 μΩ·cm降低到我们研制的3 μΩ·cm。这些工艺对于电镀低电阻率的16 nm厚的Cu层是非常有用的。当使用这种铜镶嵌互连线时，可以获得三倍的速度。少

Propagation delay time in advanced logic LSI's is determined mainly by the CR time constant in the multi-level interconnection. Therefore, reduction of interconnection resistance with employing Cu layer is the most important factor to manufacture high speed LSI's. Although resistivity increases markedly with decreasing line width in the Cu interconnection layers, specifically at widths below 100 nm, little works have been done for the reduction of resistivity. Quantitative measurement of resistivity is also difficult in this interconnection layer. This work indicates clearly that resistance of 60 nm wide Cu Damascene line is determined by that of 16 nm thick nucleated Cu layer.Resistivity is 3 μΩ-cm in 300 nm thick Cu layers. It increases rapidly with decreasing thickness and reaches 12 μΩ-cm at thickness of 50 nm. This increase is due to the reduction of grain size and (200) orientation, increasing of stress and also to the inhomogeneous nucleation. It has been found that resistivity … More of 16 nm thick nucleated layer is important in the manufacturing of 60 nm wide Cu Damascene interconnection lines. Low resistivity 16 nm thick Cu interconnection layer can be electroplated when the nucleation on the seed layer can be achieved uniformly. Uniform nucleation has practically been studied with employing newly developed electrolytic solution of copper-hexafluoro-silicate. This improvement can also be attained by the surface cleaning of Cu seed layer, optimization of additive contamination, deposition and formation of low stress seed layer and also by the deposition of low stress barrier layer instead of conventional barrier layer of TaN. Relation of these process parameters with the resistivity of thin Cu layer has been studied quantitatively in this work.As a result of these fundamental research works, resistivity of 50 nm thick Cu layer decreases from 12 μΩ-cm in conventional layer to 3 μΩ-cm in this layer developed by us. These processes are very useful for the electroplating of low resistivity 16 nm thick Cu layers. Three time higher speeds can be attained when this Cu Damascene interconnection line is used. Less