Research on False Test Avoidance for LSI Yield Improvement

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In VLSI testing, test input data often causes high switching activity, which results in IR-drop, and thus signal propagation delay. It has been shown that a 10% supply voltage drop may increase path delay by 15%. This delay increase often causes faulted test response to be loaded into flip-flops in capture mode. As a result, it is especially important to reduce test-induced switching activity in capture mode. This research was focused on solving the yield loss problem by reducing test-induced switching activity. The achievements of this research are as follows:I. Basic TechniquesA technique for handling intermediate faulty voltages in a deep-submicron circuit has been proposed. In addition, a method for speeding up fault simulation by using both complied-code and event-driven techniques have been developed.II. At-Speed Test TechniquesFaults existing between two synchronous clock domains need to be detected in order to improve test quality. We proposed a inter-clock-domain at-speed test controller, which can be used in both ATE-based external test and BIST.III. X-Bit Identification TechniquesSeveral techniques for identifying don't care bits (X-bits) from a fully-specified test set without any fault coverage loss have been developed. In addition to fault coverage, the small-delay detection capability can also be preserved.IV. X-Filling TechniqueSeveral techniques for determining logic values for X-bits in test cubes so that the resulting test set has lower switching activity have been proposed. These techniques can reduce IR-drop for either a single-capture scheme or a double-capture scheme. In addition, switching activity at all cells (FFs and gates) can be targeted.V. Low-Power Test Generation TechniquesIn order to further reduce capture switching activity, we proposed an ATPG method for directly generating logic bites for the purpose of low test power. Anew concept, called capture-conflict (C-conflict), was introduced for this low-power test generation.