Power Adjustment Testing for Next-Generation Low-Power LSI Circuits

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There are two major problems in LSI testing, namely decreasing test yield due to excessive delay along sensitized paths and decreasing test quality due to inadequate delay along sensitized paths. In this research, a novel scheme has been established, which dynamically adjusts regional power dissipation in the neighborhood of sensitized paths to minimize its impact on test yield and test quality. This scheme of power adjustment testing is expected to contribute to higher test yield and better test quality.