Logic synthesis using EXOR gates
Logic synthesis using EXOR gates
批准号:
02805046
负责人:
SASAO Tsutomu
金额:
$1.28万
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (C)
财政年份:
1990
资助国家:
日本
项目状态:
已结题
起止时间:
1990 至 1991
中文摘要
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英文摘要
Automatic logic synthesis tools are extensively used in LSI design. Most logic synthesis tools use AND and OR gates as basic logic elements. Arithmetic and error correcting circuits can be realized with many fewer gates if EXOR gates are available as well as AND and OR gates. Such circuits can be derived from AND-EXOR two-level circuits. So the minimization of Exclusive-OR sum-of-products expressions(ESOPs), which corresponds to the minimization of AND-EXOR two-level circuits, is important. ESOPs require fewer products than SOPs to realize randomly generated functions and symmetric functions. To realize an arbitrary function of 6 variables, an ESOP requires only 16 products, whereas an SOP requires 32 products. Although there exists a class of functions whose ESOP realizations require more production SOPS, the ESOP's are important tool in efficient logic design. The number of products in AND-OR two-level circuits can be reduced by adding decoders to the inputs(i. e., AND-OR PLAs with t … More wo-bit decoders). In a similar way, the number of products in AND-EXOR two-level circuits can be reduced by adding decoders to the inputs(i. e., AND-EXOR PLAs with two-bit decoders). We compared the number products and literals to represent arithmetic functions of 8-inputs by AND-OR circuits and AND-EXOR circuits with one and two-bit decoders, where a one-bit decoder generates true and complemented variables. Circuits based on ESOPs required fewer gates than the ones based on SOPS. The minimization of AND-EXOR circuits with decoders can be done by the minimization of ESOPs with multiple-valued inputs.The first result is EXMIN2, a heuristic simplification algorithm for AND-EXOR expression with multiple-valued inputs. The algorithm iteratively reduces the number of the products in ESOPs as the first objective, and then reduces the number of the literals as the second objectives. Experimental results show that ESOPs usually require fewer products and connections than SOPs to represent arithmetic functions. The-second result is a design method for AND-OR-EXOR circuits. In the most technologies, EXORs are more expensive than ORs. To reduce the cost, we developed a method to replace some of the EXORs with ORs in ESOPs without increasing the number of the products. Less
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N. Koda and T. Sasao: "On the number of product terms of AND-EXOR minimumexpressions,(in Japanese)" IEICE Technical paper. FTS91-22. (1991)
N. Koda 和 T. Sasao:“关于 AND-EXOR 最小表达式的乘积项的数量,(日语)”IEICE 技术论文。
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T. Sasao: "Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams" IEICE Technical Paper. VLD91-109. (1991)
T. Sasao:“使用多处决策图优化多值 AND-EXOR 表达式”IEICE 技术论文。
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T.Sasao: "Bounds on the average number of products in the minimum sum-of-products expressions for multiple-valued input two-valued output functions" IEEE Trans.on Comput.40. 645-651 (1990)
T.Sasao:“多值输入二值输出函数的最小乘积和表达式中乘积平均数量的界限”IEEE Trans.on Comput.40。
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T. Sasao: "Exclusive-Or sum-of-products expressions: their properties and minimization algorithms" IEICE Technical Paper. VLD90-87. (1990)
T. Sasao:“异或积和表达式:它们的属性和最小化算法”IEICE 技术论文。
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T. Sasao and D. Brand: "On the minimization of AND-EXOR expressions" IEICE Technical Paper. VLD90-88. (1990)
T. Sasao 和 D. Brand:“关于 AND-EXOR 表达式的最小化”IEICE 技术论文。
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共 28 条
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财政年份:2000
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Decomposition of Large-Scale Logic Functions
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A Research on the development of a logic synthesis system using EXOR gates
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A Research on the Representation and Manipulation of Logical Expressions using Ternary Decision Diagrams
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财政年份:1990
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