Studies on logic design and testing methodology for very high performance VLSIs

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Deep sub-micron and high-performance circuits often have a delay variation problem caused by noise, process, and power. Most of manufacturing defects of the circuits cause timing-related failures too. In order to guarantee high reliability of the high performance circuits, we investigated design and test issues on timing failures. Path delay fault model is known as one of a well-known timing failure to be tested. In test generation for path delay faults, it is important to identify untestable paths prior to test generation. We first developed a method to identify untestable paths of a given circuit. Though methods proposed earlier required long time to process a circuit with large number of paths, our method could deal with such a circuit with a short computation time without sacrificing the ability of untestable path identification. In addition, we proposed a method to extract a set of paths which should be tested and more likely be faulty. Next we considered the problem of validating flip-flop data hold time requirements in synchronous sequential circuits, which is different from flip-flop set-up time errors like path delay faults. Three fault models and a test generation procedure were proposed that are related to the presence of short paths in the circuit. Finally we investigated a methodology of design and test for detecting timing faults of high performance circuits using a low-speed LSI tester. In case of using a low-speed tester, test compression is a necessary technique. In order to obtain a test set which can be highly compressed, we developed a method for identifying don't care inputs of a given test set. We also proposed a method to compress a test set with don't care inputs and showed the effectiveness of the proposed method.