A Research on the development of a logic synthesis system using EXOR gates
A Research on the development of a logic synthesis system using EXOR gates
批准号:
05558032
负责人:
SASAO Tsutomu
金额:
$2.62万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
财政年份:
1993
资助国家:
日本
项目状态:
已结题
起止时间:
1993 至 1995
中文摘要
本文研究了五类与-异或表达式:FPRM(Fixed Polarity Reed-Muller expression)、KRO(Kronecker expression)、PSDKRO(pseudo-Kronecker expression)、GRM(Generalized Reed-Muller expression)和ESOP(EXOR sum-of-products expression)。在这些表达式中,员工持股计划需要的产品最少,但优化是困难的。开发了一个求解ESOP的启发式极小化程序EXMIN 2,对于输入数较少的ESOP问题,通过穷举法可以得到一个精确的最小ESOP.我们得到了所有最小的员工持股计划,最多5个变量。我们还开发了一个简化程序使用的结果,确切的最小ESOP。我们还开发了一个精确的最小化方法,使用BDD的员工持股计划。这个程序对于n=6的函数很有用。GRM是ESOP的一个子类。我们发明了一种易于测试的GRM实现,并开发了 关于我们 一种基于BDD的GRM精确最小化方法和一种基于迭代改进的启发式简化方法,FPRM是GRM的子类。本文提出了一种利用多端EXOR三元决策图求取精确最小FPRM的方法,并成功地将90个以上输入和多个输出的FPRM最小化。我们开发了一个最小化程序PSDKRO使用ETDD。该方法比EXMIN 2算法速度快得多,可作为ESOP最小化算法的预处理器。2.用EXOR门综合多电平逻辑网络提出了一种用AND、OR、EXOR和反相器综合多电平逻辑网络的方法。该设计方法首先由给定的函数生成一个伪克罗内克决策图(PKDD),然后生成由AND、OR、EXOR和反相器组成的多级逻辑网络。最后,它简化了网络,通过使用本地转换。MCNC基准测试的实验结果表明,该方法适用于算术网络的设计。少
英文摘要
In this research, we developed a logic synthesis system using EXOR gates.1.Optimization of various AND-EXOR expressionsWe considered five classes of AND-EXOR expressions : FPRM(Fixed Polarity Reed-Muller expression), KRO(Kronecker expression), PSDKRO(pseudo-Kronecker expression), GRM(Generalized Reed-Muller expression), and ESOP(EXOR sum-of-products expresion). ESOPs require the fewest products among these expressions, but the optimization is, difficult. We developed EXMIN2, a heuristic minimization program for ESOPs.For the ESOPs with small number of inputs, we can obtain an exact minimum ESOPs by using exhaustive methods. We obtained all the minimum ESOPs up to 5 variables. We also developed a simplification program using the results of exact minimum ESOPs. We also developed an exact minimization method for ESOPs using BDDs. This program is useful for the functions with up to n=6 variables.GRM is a sub-class of ESOPs. We invented an easily testable realization for GRMs, and developed … More an exact minimization method for GRMs by using BDDs, and a heuristic simplification method using iterative improvement method.FPRM is a sub-class of GRMs. We developed a method to obtain exact minimum FPRMs by using multi-terminal EXOR ternary decision diagrams, and successfully minimized the FPRMs with more than 90 inputs and many outputs.PSDKRO in a sub-class of ESOPs. We developed a minimization program for PSDKROs by using ETDDs. This method is much faster than EXMIN2, and can be used as pre-processor for ESOP minimization algorithm.2.Synthesis of multi-level logic networks using EXOR gates.We developed a method to derive multi-level logic networks using AND,OR,EXOR and inverters. The design method first generates a Pseudo-Kronecker decision diagram(PKDDs)from given functions.Then, it generates multi-level logic networks consisting of AND,OR,EXOR and inverters. Finally, it simplifies the networks by using local transformation. Experimental results using MCNC benchmarks show that our method is suitable for the design of arithmetic networks. Less
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Tsutomu Sasao and Jon T.Butler: "A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion" ISMVL-94. 97-106 (1994)
Tsutomu Sasao 和 Jon T.Butler:“一种通过伪克罗内克扩展的查找表型 FPGA 设计方法”ISMVL-94。
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T.Sasao and D.Debnath: "An exact minimization algorithm for generalized Reed-Muller expressions IEEE Asia-Pacific Conference on Circuits and Systems" APCCAS'94. 460-465 (1994)
T.Sasao 和 D.Debnath:“广义 Reed-Muller 表达式的精确最小化算法 IEEE 亚太电路与系统会议”APCCAS94。
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T.Sasao: "Optimization of pseudo-Kronecker expressions using multiple-place decision diagrams" IEICE Transactions on Information and Systems. E76-D. 562-570 (1993)
T.Sasao:“使用多处决策图优化伪克罗内克表达式”IEICE Transactions on Information and Systems。
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N.Koda and T.Sasao: " "LP equivalence class of logic functions, "" IFIP 10.5 Workshop on Application of the Reed-Muller expansion in Circuit Design, Sept.1993.
N.Koda 和 T.Sasao:““逻辑函数的 LP 等价类”,“IFIP 10.5 电路设计中 Reed-Muller 扩展应用研讨会”,1993 年 9 月。
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N.Koda and T.Sasao: " "EXBOUND : A minimization algorithm for multipleoutput AND-EXOR expressions, "" Technical Report, IEICE Japan, FTS93-35, Oct.1993.
N.Koda 和 T.Sasao:“EXBOUND:多输出 AND-EXOR 表达式的最小化算法”,技术报告,IEICE 日本,FTS93-35,1993 年 10 月。
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共 59 条
Logic synthesis using linear transformation and memories.
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批准号:23300016
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$5.82万
-
财政年份:2011
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负责人:SASAO Tsutomu
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依托单位:
A study on the realization and application of content-addressable memory using general-purpose memory
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批准号:19300013
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$5.08万
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财政年份:2007
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负责人:SASAO Tsutomu
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依托单位:
Research on programmable logic elements using the virtual wiring and their logic synthesis method
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批准号:14380146
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$5.57万
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财政年份:2002
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负责人:SASAO Tsutomu
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依托单位:
Development of hardware logic simulator using decision diagrams
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批准号:12558030
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$4.93万
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财政年份:2000
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负责人:SASAO Tsutomu
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依托单位:
Studies on logic design and testing methodology for very high performance VLSIs
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批准号:11694168
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$2.18万
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财政年份:1999
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负责人:SASAO Tsutomu
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依托单位:
Decomposition of Large-Scale Logic Functions
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批准号:10680360
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$1.66万
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财政年份:1998
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负责人:SASAO Tsutomu
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依托单位:
A Research on the realization of three-level logic networks
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批准号:08680374
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$1.54万
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财政年份:1996
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负责人:SASAO Tsutomu
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依托单位:
A Research on the Representation and Manipulation of Logical Expressions using Ternary Decision Diagrams
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批准号:05680279
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项目类别:Grant-in-Aid for General Scientific Research (C)
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资助金额:$1.28万
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财政年份:1993
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负责人:SASAO Tsutomu
-
依托单位:
Development of A Silicon Complilation System for Rewritable LSIs
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批准号:02555073
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项目类别:Grant-in-Aid for Developmental Scientific Research (B)
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资助金额:$2.82万
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财政年份:1990
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负责人:SASAO Tsutomu
-
依托单位:
Logic synthesis using EXOR gates
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批准号:02805046
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项目类别:Grant-in-Aid for General Scientific Research (C)
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资助金额:$1.28万
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财政年份:1990
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负责人:SASAO Tsutomu
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依托单位:
Decomposition of large-scale Programmable logic arrays
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批准号:63550274
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项目类别:Grant-in-Aid for General Scientific Research (C)
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资助金额:$1.15万
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财政年份:1988
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负责人:SASAO Tsutomu
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依托单位:
海外基金