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A Research on the realization of three-level logic networks

A Research on the realization of three-level logic networks
三层逻辑网络的实现研究
批准号:
08680374
负责人:
SASAO Tsutomu
金额:
$1.54万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
1996
资助国家:
日本
项目状态:
已结题
起止时间:
1996 至 1997

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(1) AND-OR-EXOR three-level networks.We considered design methods for AND-OR-EXOR three-level networks, where single two-input EXOR gate is used for each output. The network realizes an EXOR of two sum-of-products expressions (EX-SOP), F1 F2, where F1 and F2 are sum-of-products expressions (SOPs). The problem is to minimize the total number of different products in F1 and F2.(2)OR-AND-OR three-level networks.We considered the number of gates to realize logic functions by OR-AND-OR three-level networks under the condition that both true and complemented variables are available, and each gate has no fan-in and fan-out constraints. We show that an arbitrary n-variable function can be realized by an OR-AND-OR three-level network with at most 2^{r+1}+1 gates、where n=2r and r are integers. We developed a heuristic algorithm to design OR-AND-OR three-level networks, and compared the number of gates for three-level networks with two-level ones.(3) Bi-decomposition.A logic function f has a disjoint bi-decomposition iff f can be represented as f=h(g_1(X_1), g_2(X_2)), where X_1 and X_2 are disjoint set of variables, and h is an arbitrary two-variable logic function. We showed a fast method to find bi-decompositions without using decomnposition chart. Also, we enumerated the number of functions having bi-decompositions. When the function has a bi-decomposition, three-level network is easy to derive.(4)Generalized Reed-Muller expressionsA generalized Reed-Muller Expression (GRM) is obtained by negating some of the literals in a positive polarity Reed-Muller expression (PPRM).There are at most 2^{n{2^{n-1}} different GRMs for an n-variable function. A minimum GRM is one with the fewest products. We showed some properties and a minimization algorithm for GRMs. The minimization algorithm is based on binary decision diagrams. We also developed GRMIN2, heuristic minimization program for GRMs. We also developed an easily testable realization for GRMs.
期刊论文(0)
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会议论文
T.Sasao and D.Debnath: "Generalized Reed-Muller expressions : Complexty and an exact minimization algorithm, "" IEICE Transactions. Vol.E79-A,No.12. 2123-2130 (1996)
T.Sasao 和 D.Debnath:“广义 Reed-Muller 表达式:复杂性和精确最小化算法”,IEICE Transactions. Vol.E79-A,No.12. 2123-2130 (1996)
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通讯作者:
J.T.Butler and T.Sasao: " "Average number of nodes in binary decision diagrams of Fibonacci functions, "" Fibonacci Quarterly. (accepted for publication).
J.T.Butler 和 T.Sasao:““斐波那契函数二元决策图中的平均节点数”,《斐波那契季刊》。
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T.Sasao and J.T.Butler: "Planar decision diagrams for multiple-valued functions" Multiple-valued Logic:An International Journal. 1・1. 39-46 (1996)
T.Sasao 和 J.T.Butler:“多值函数的平面决策图”多值逻辑:国际期刊 1・1 (1996)。
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J.T.Butler and T.Sasao: "Aberage number of nodes in binary decision diagrams of Fibonacci functions" Fibonacci Quarterly. Vol.34.5. 413-422 (1996)
J.T.Butler 和 T.Sasao:“斐波那契函数二元决策图中的节点数量”斐波那契季刊。
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11
    Logic synthesis using linear transformation and memories.
    A study on the realization and application of content-addressable memory using general-purpose memory
    • 批准号:
      19300013
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $5.08万
    • 财政年份:
      2007
    • 负责人:
      SASAO Tsutomu
    • 依托单位:
    Research on programmable logic elements using the virtual wiring and their logic synthesis method
    • 批准号:
      14380146
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $5.57万
    • 财政年份:
      2002
    • 负责人:
      SASAO Tsutomu
    • 依托单位:
    Development of hardware logic simulator using decision diagrams
    • 批准号:
      12558030
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $4.93万
    • 财政年份:
      2000
    • 负责人:
      SASAO Tsutomu
    • 依托单位: