Logic synthesis using linear transformation and memories.

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In routers for the internet and computer virus scanners, high-speed pattern matching is indispensable. In such applications, patterns must be modified frequently. To perform such operation, CAMs (Content Addressable Memories) have been used. Unfortunately, CAMs dissipate high power, and large-scale CAMs are very expensive. In this research, we developed a method to decompose an index generation function into linear and non-linear parts. Non-linear parts are realized by memories, where the number of input variables are reduced. With this method, we can implement a large-scale pattern matching circuit by using general-purpose memories. Thus, obtained circuits are low-cost and low-power.