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A high performance on-chip data transfer technique using pulse modulation signals

使用脉冲调制信号的高性能片上数据传输技术

基本信息

批准号：
07455151
负责人：
IWATA Atsushi
金额：
$ 4.61万
依托单位：
HIROSHIMA UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1995
资助国家：
日本
起止时间：
1995 至 1996
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07455151/
关键词：
PULSE MODULATION PULSE WIDTH MODULATION PULSE PHASE MODULATION DATA TRANSFER CMOS TECHNOLOGY TRANSCEIVER CIRCUIT GATE ARRAY 回路設計位相検出回路位相同期回路変復調回路

项目摘要

In order to improve a bit rate and power efficiency for on-chip data transfer systems, data transceiver circuits using pulse modulation signals were developed. A pulse phase modulation (PPM) system has higher performance comparing with a pulse width modulation (PWM). However, PPM requires precision phase synchronizing circuit which consumes much power and chip area. A PWM data transceiver circuits were designed by using a 250-MHz, 4-phase delay locked loop technique, and a 1ns time resolution was obtained. It realizes 1Gbits/sec data rate with low power dissipation. For implementations by gate arrays, a PWM transceiver circuit utilizing only logic gates was developed. These transceiver circuits were described by hardware description language (HDL), and synthesized by logic synthesis tools. The circuits were evaluated by logic simulation (Verilog-XL) and circuits simulation (HSPICE). The PWM transceiver test chip was designed using a 0.5mum CMOS process. A Mask Layout was designed by standard cell design tools. A measurement technique for a 1ns timing accuracy and a bit error rate of the PWM transceiver was achieved using an arbitrary wave from generator and a logic analyzer. The measurements results of the test chip shows that maximum clock frequency and timing accuracy are almost as the same as the simulation results.

为了提高片上数据传输系统的比特率和功率效率，开发了使用脉冲调制信号的数据收发电路。与脉宽调制(PWM)相比，脉冲相位调制(PPM)系统具有更高的性能。然而，PPM需要精确的相位同步电路，这会消耗大量的功耗和芯片面积。采用250 MHz四相延迟锁相环技术设计了一种脉宽调制数据收发电路，获得了1 ns的时间分辨率。它以低功耗实现了1Gbit/s的数据速率。为了通过门阵列实现，开发了一种仅使用逻辑门的PWM收发电路。这些收发电路用硬件描述语言(HDL语言)描述，并用逻辑综合工具进行综合。通过逻辑仿真(Verilog-XL)和电路仿真(HSPICE)对电路进行了评估。脉宽调制收发测试芯片采用0.5um工艺设计。掩模布局由标准单元设计工具设计。利用来自发生器和逻辑分析仪的任意波形，实现了对PWM收发信机1 ns定时精度和误码率的测量技术。测试芯片的测试结果表明，最大时钟频率和时序精度与仿真结果基本一致。