A high performance on-chip data transfer technique using pulse modulation signals

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In order to improve a bit rate and power efficiency for on-chip data transfer systems, data transceiver circuits using pulse modulation signals were developed. A pulse phase modulation (PPM) system has higher performance comparing with a pulse width modulation (PWM). However, PPM requires precision phase synchronizing circuit which consumes much power and chip area. A PWM data transceiver circuits were designed by using a 250-MHz, 4-phase delay locked loop technique, and a 1ns time resolution was obtained. It realizes 1Gbits/sec data rate with low power dissipation. For implementations by gate arrays, a PWM transceiver circuit utilizing only logic gates was developed. These transceiver circuits were described by hardware description language (HDL), and synthesized by logic synthesis tools. The circuits were evaluated by logic simulation (Verilog-XL) and circuits simulation (HSPICE). The PWM transceiver test chip was designed using a 0.5mum CMOS process. A Mask Layout was designed by standard cell design tools. A measurement technique for a 1ns timing accuracy and a bit error rate of the PWM transceiver was achieved using an arbitrary wave from generator and a logic analyzer. The measurements results of the test chip shows that maximum clock frequency and timing accuracy are almost as the same as the simulation results.