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A 3 Dimensional Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains

A 3 Dimensional Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains
利用无线互连实现超级大脑的 3 维集成方案
批准号:
15106007
负责人:
IWATA Atsushi
金额:
$71.64万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (S)
财政年份:
2003
资助国家:
日本
项目状态:
已结题
起止时间:
2003 至 2007

项目摘要

项目成果

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中文摘要
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英文摘要
Research Objectives:3D integration technologies using wireless interconnections and object recognition systems Research achievements:(1). Chip-to-chip wireless interconnection and 3D integration deviceschip-to-chip wireless interconnection using electromagnetic induction between coupled inductors was proposed, and test circuits were designed and fabricated. Bit rate of 1Gb/s was achieved with 1mW power dissipation; Bit rate of 2.4Gb/s was achieved with high speed design.Three dimensional integration technology utilizing wireless interconnection using on-chip antenna and inductor coupled interconnection, named 3DCSS was proposed. Basic scheme and prototype systems were designed and fabricated. High performance image processing was realized with 3DCSS.Standing wave oscillator using inductor termination and coupling was proposed and a test chip was designed and fabricated with an 0.18um CMOS technology. 10GHz high quality oscillation signal with low phase noise was obtained.MOS device mod … More el (HiSIM) using surface potential was proposed, and highly accurate description capability with small number of parameters was effective for larger than 10GHz frequency range RF circuit applications.(2) Highly cognitive systems using chip-to-chip wireless interconnectionAn associative memory using analog and digital combined circuit techniques was developed, and highly speed operation with low power dissipation were confirmed. Highly functional, high performance pattern matching which was essential for detection, tracking and recognition of objects in image signals was implemented utilizing the associative memories.3D prototype system integrating three kinds of image processing chips was implemented, and expected data transfer speed was obtained. Low voltage operated low noise amplifier and high performance VCO were also developed for basic circuit blocks.(3) Processing algorithm for implementing brain functions and systemsLearning algorithm based on a human brain was implemented in an associative memory. By using the algorithm, a memory based learning model was proposed and its effectiveness for image recognition was confirmed. Less
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期刊:
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发表时间: 2005
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