A Study of Silicon (PIN) Pixel detectors

本项目主要研究和开发基于PIN二极管结构的硅像素探测器，用于带电粒子和光子的探测。该项目还旨在开发像素探测器的基本技术。pMOS像素探测器原型在KEK成功地测试了π介子束。制造和测试了三种pMOS器件的变体，以提高器件的速度，增加复位每个像素的能力，并改善响应（可见光波长较短的光子）。SOI像元探测器是在SOI晶片上制作像元探测器的一种新的思路。通过在SOI晶片的高阻硅层中形成PIN像素单元和在低阻SOS层上制造读出微电子器件，解决了单片像素器件的问题。制作SOI像素器件的测试结构以测试穿过SOI晶片的绝缘体的PIN像素单元与SOS层上的读出电子器件之间的接触。结果表明，在SOS晶片上的读出电子器件工作正常的情况下，仍然需要调整一些工艺参数来制作像素结构和接触。亚微米CMOS硅工艺由于氧化层较薄，因此被推测为更抗辐射。我们的测试由SII 0.8微米（低温）工艺制造的晶体管显示出有希望的结果的阈值漂移的晶体管。然后，我们制作了一个128通道的CMOS CMOS CMOS VLSI，我们已经在另一个项目开发，通过0.8微米工艺。这些芯片现在正在准备进行辐照测试。在SII成功地测试了实际探测器尺寸的50微米间距的焊料凸点接合。

The project is to study and develop Silicon pixel detectors based on the PIN diode structure for detection of charged particles and photon. The project also aims at development of basic technologies for the pixel detectors. A pMOS pixel detector prototype was tested successfully for a pion beam at KEK.Three variations of the pMOS device were fabricated and tested to improve the speed of the device, to add a capability to reset each pixel and to improve the response (ovisible photon of shorter wave length. The SOL pixel detector is a new idea to fabricate a pixel detector on the SOI wafer. It should solve the problems of the monolithic pixel device by forming the PIN pixel cells in the high resistive silicon layer of the SOI wafer and fabricating the readout micro electronics on the low resistive SOS layer. Test structures of the SOI pixel device were made to test the contact through the insulator of the SOL wafer between a PIN pixel cell and a readout electronics on the SOS layer. The result showed that some tuning of process parameters were still needed to make the pixel structure and contact, while the readout electronics on the SOS wafer worked as expected. The sub-micron CMOS silicon processes had been speculated to be more radiation-hard because of the thinner oxide-layers. Our test of transistors fabricated by the SII 0.8 micron (low temperature) process showed promising results on the threshold shift of the transistors. We then fabricated a 128ch CMOS preamplifier VLSI, which we have developed in another project, by the 0.8 micron process. The chips are now being prepared for an irradiation test. A solder bump bonding of 50 micron pitch for an actual detector size was also tested successfully at SII.