A Study of Silicon (PIN) Pixel detectors

该项目是研究和开发基于PIN二极管结构的硅像素探测器，用于探测带电粒子和光子。该项目还旨在开发像素探测器的基本技术。一个PMOS像素探测器样机在KEK成功地测试了一束π子束。制作并测试了PMOS器件的三种变体，以提高器件的速度，增加重置每个像素的能力，并改善响应(更短波长的可见光子)。SOL像素探测器是在SOI晶片上制作像素探测器的一种新思路。在SOI硅片的高阻硅层中形成PIN像素单元，在低阻SOS层上制作读出微电子器件，可以解决单片像素器件的问题。制作了SOI像素器件的测试结构，以测试通过SOL晶片的绝缘体在PIN像素单元与SOS层上的读出电子之间的接触。结果表明，当SOS晶片上的读出电子器件工作正常时，仍需对工艺参数进行一些调整以使像素结构和接触。据推测，由于氧化层较薄，亚微米级的cmos硅工艺更耐辐射。我们对采用SiI 0.8微米(低温)工艺制造的晶体管的测试表明，晶体管的阈值漂移取得了令人满意的结果。然后，我们用0.8微米的工艺制作了我们在另一个项目中开发的128路CMOS前置放大器VLSI。这些芯片现在正在为辐射测试做准备。对于实际探测器尺寸，50微米间距的焊料凸点键合也在SII上成功测试。

The project is to study and develop Silicon pixel detectors based on the PIN diode structure for detection of charged particles and photon. The project also aims at development of basic technologies for the pixel detectors. A pMOS pixel detector prototype was tested successfully for a pion beam at KEK.Three variations of the pMOS device were fabricated and tested to improve the speed of the device, to add a capability to reset each pixel and to improve the response (ovisible photon of shorter wave length. The SOL pixel detector is a new idea to fabricate a pixel detector on the SOI wafer. It should solve the problems of the monolithic pixel device by forming the PIN pixel cells in the high resistive silicon layer of the SOI wafer and fabricating the readout micro electronics on the low resistive SOS layer. Test structures of the SOI pixel device were made to test the contact through the insulator of the SOL wafer between a PIN pixel cell and a readout electronics on the SOS layer. The result showed that some tuning of process parameters were still needed to make the pixel structure and contact, while the readout electronics on the SOS wafer worked as expected. The sub-micron CMOS silicon processes had been speculated to be more radiation-hard because of the thinner oxide-layers. Our test of transistors fabricated by the SII 0.8 micron (low temperature) process showed promising results on the threshold shift of the transistors. We then fabricated a 128ch CMOS preamplifier VLSI, which we have developed in another project, by the 0.8 micron process. The chips are now being prepared for an irradiation test. A solder bump bonding of 50 micron pitch for an actual detector size was also tested successfully at SII.