A Study of Silicon (PIN) Pixel detectors

本课题研究开发基于PIN二极管结构的硅像素探测器，用于探测带电粒子和光子。该项目还旨在开发像素探测器的基础技术。在KEK上成功地测试了pMOS像素探测器原型。为了提高器件的速度，增加每个像素的重置能力，并提高对短波长的可见光子的响应，制作了三种不同的pMOS器件并进行了测试。SOL像素探测器是在SOI晶圆上制作像素探测器的一种新思路。在SOI晶圆的高阻硅层上形成PIN像素单元，在低阻SOS层上制造读出微电子器件，解决了单片像素器件的问题。制作了SOI像素器件的测试结构，用于测试PIN像素单元与SOS层上读出电子器件之间通过SOL晶片绝缘体的接触。结果表明，在SOS晶圆上的读出电子器件工作正常的情况下，仍需要对工艺参数进行一些调整以使像素结构和接触正常。据推测，亚微米CMOS硅工艺的抗辐射能力更强，因为氧化层更薄。我们对SII 0.8微米（低温）工艺制作的晶体管进行了测试，在晶体管的阈值位移方面取得了令人满意的结果。然后我们制作了一个128ch CMOS前置放大器VLSI，这是我们在另一个项目中开发的，采用0.8微米工艺。这些芯片现在正准备进行辐照试验。在SII也成功地测试了实际探测器尺寸的50微米间距的焊料凹凸键合。

The project is to study and develop Silicon pixel detectors based on the PIN diode structure for detection of charged particles and photon. The project also aims at development of basic technologies for the pixel detectors. A pMOS pixel detector prototype was tested successfully for a pion beam at KEK.Three variations of the pMOS device were fabricated and tested to improve the speed of the device, to add a capability to reset each pixel and to improve the response (ovisible photon of shorter wave length. The SOL pixel detector is a new idea to fabricate a pixel detector on the SOI wafer. It should solve the problems of the monolithic pixel device by forming the PIN pixel cells in the high resistive silicon layer of the SOI wafer and fabricating the readout micro electronics on the low resistive SOS layer. Test structures of the SOI pixel device were made to test the contact through the insulator of the SOL wafer between a PIN pixel cell and a readout electronics on the SOS layer. The result showed that some tuning of process parameters were still needed to make the pixel structure and contact, while the readout electronics on the SOS wafer worked as expected. The sub-micron CMOS silicon processes had been speculated to be more radiation-hard because of the thinner oxide-layers. Our test of transistors fabricated by the SII 0.8 micron (low temperature) process showed promising results on the threshold shift of the transistors. We then fabricated a 128ch CMOS preamplifier VLSI, which we have developed in another project, by the 0.8 micron process. The chips are now being prepared for an irradiation test. A solder bump bonding of 50 micron pitch for an actual detector size was also tested successfully at SII.