Research on Intelligent Design Verification of VLSIs

我们一直专注于一种智能设计验证方法，适用于VLSI设计与教育中心（VDEC）的芯片制造服务。传统上，布局验证是基于模式处理的。然而，对于初学者的技能提升和设计质量的提高来说，需要一种相当于专业设计师的智能布局验证方法。在本研究中，我们重点研究了供电线路的设计和质量。我们从布局中提取电力线，并根据连接到它们的晶体管尺寸估计线路的最大电流。电流浓度和电源线噪声来自最大电流，并报告给设计人员。为此，我们研究了片上电力线噪声的实时测量技术。我们采用了基于电压采样器的片上电压监测器，并采用了改进的开关电容电路技术。对于标准的0.6 um CMOS技术，在时间和电压上的分辨率分别为1[ns]和20[mV]。我们用电压监测器和测压元件制作了模拟功能块的测试芯片，并证明了上述电压监测器可以有效地测量电源反弹。我们提出了“片上电压扫描路径技术”来实时监测芯片上的功率反弹。电压扫描路径技术由电压监测器以移位寄存器的方式串联而成，与边界扫描路径技术类似。使用这种技术，仅用有限的IO引脚就可以监测电力线每个主要位置的功率反弹。该技术有望在不久的将来用于密度较大的LSls的失效分析。

We have been focusing on an intelligent design verification method, that can be applicable to chip fabrication services of VLSI Design and Education Center (VDEC) . Conventionally, layout verification has been based on pattern processing. It is , however, intelligent layout verification method, which is equivalent to that of expert designers is necessary for beginners' skill up along with design quality enhancement.In this research, we have focused on designs and quality of power supply lines. We extract power lines from layout and estimate maximum current of lines based on transistor sizes connected to them. Current concentration and power line noise are derived from the maximum current and are reported to designers. To achieve this, we have examined real-time measurement technique of on-chip power line noise. We employed on-chip voltage monitor based on a voltage sampler with a regenerative comparator using a modified switched capacitor circuit technology. The resolutions in time and voltage are about 1[ns] and 20[mV] for a standard O.6um CMOS technology. We have fabricated test chips with the voltage monitors and load cells for emulating function blocks and demonstrated that above voltage monitor is effectively measure power supply bounce. We have proposed "on-chip Voltage scan-path technique" for monitoring real-time power bounce on chip. The voltage scan-path technique consists of voltage monitors connected serially as shift-register manner, which is just similar to boundary scan-path technique. Using this technique, power bounce in every major position of power lines can be monitored with only limited IO pins. This technique is expected to be necessary for failure analysis of denser LSls in near future.