Research on Processor architecture based on pseudo-asynchronous concept

在本研究中，我们研究了伪异步设计，与传统的同步系统相比，它可以在不增加硬件开销的情况下达到平均性能。此外，还设计了基于伪异步概念的数据路径。在伪异步数据路径中，管道中的数据流由完成信号控制。但是，由于以往设计中完井检测的生成延迟，限制了整体速度。在我们的研究中，为了使完井信号的生成速度与计算速度一样快，提出了完井预测方法。以纹波进位加法器（RCA）和进位前瞻加法器（CLA）为例，研究了完井预测方法的应用。电路仿真结果表明，与传统同步加法器相比，平均速度提高20% ~ 66%。这种加法器被设计为不费多大力气就可以实现为LSI IP（知识产权）。我们一直致力于通过芯片间/芯片内总线接口的数据编码进行低功耗LSI设计的研究工作。然而，当我们将这种方法应用于同步系统时，必须解决由于编码导致的数据传输延迟问题。在异步或伪异步系统中，由不具有恒定延迟的块构成，总线接口产生的延迟时间并不重要。在这一年中，我们将研究重点集中在无冗余位的数据编码上，这种编码方式除了驱动电路外，对总线接口的改变最小。通过对数据传输的统计计算，实现编码码本的实时更新。因此，虽然没有使用冗余位，但总线中高达20%的信号转换被切断。

In this research, pseudo asynchronous design, which can achieve an average-case performance without much hardware overhead compared with conventional synchronous system, is studied. Furthermore, datapath based on the pseudo asynchronous concept is designed.In pseudo asynchronous datapath, data flow in pipeline is controlled by a completion signal. However, due to the generation delay of completion detection in previous design, the overall speed was limited. n our research, to generate the completion signal as fast as the alculation speed, completion prediction method is proposed. As a case tudy, the completion prediction method is applied to both ripple carry adder (RCA) and carry lookahead adder (CLA). Circuit simulation results show that speed improvement is 20% to 66% in average case compared with corresponding conventional synchronous adders. Such a kind of adder is designed to be implemented as LSI IP (Intellectual Property) without much effort.We have been performing research work on low power LSI design by means of data encoding on inter/intra-chip bus interface. However, when we apply this method to a synchronous system, the data transfer delay problem due to the encoding has to be solved. In asynchronous or pseudo asynchronous system, which is constructed with blocks that don't have constant delay, the delay time generated in bus interface is not critical.In this year, we concentrate our research focus on data encoding without redundant bit, which allows least changes on bus interface except for the driver circuits. With statistical calculations on data transfer, encoding codebook is updated in real time. As a result, although redundant bit is not used, up to 20% signal transitions in bus are cut off.