Research on Processor architecture based on pseudo-asynchronous concept

在本研究中，伪异步设计，它可以达到一个平均情况下的性能，而不需要太多的硬件开销相比，传统的同步系统，进行了研究。在此基础上，设计了基于伪异步概念的数据通路，在伪异步数据通路中，流水线中的数据流由一个完成信号控制。然而，由于在以前的设计中完成检测的生成延迟，整体速度受到限制。为了使完井信号的产生与计算速度相适应，提出了完井预测方法。作为一个例子，完成预测方法被应用于涟漪进位加法器（RCA）和超前进位加法器（CLA）。电路模拟结果表明，与相应的传统同步加法器相比，平均速度提高20%~ 66%。这样一种加法器被设计成LSIIP（Intellectual Property），而不需要太多的努力。我们一直在进行低功耗LSI设计的研究工作，通过在芯片间/芯片内总线接口上进行数据编码。然而，当我们将这种方法应用于同步系统时，由于编码而引起的数据传输延迟问题必须得到解决。在异步或伪异步系统中，由于系统的模块没有固定的延迟，因此总线接口产生的延迟时间并不重要，今年我们的研究重点是无冗余位的数据编码，它允许除驱动电路外对总线接口的改动最小。通过对数据传输的统计计算，编码码本被真实的实时更新。因此，虽然没有使用冗余位，但总线中高达20%的信号转换被切断。

In this research, pseudo asynchronous design, which can achieve an average-case performance without much hardware overhead compared with conventional synchronous system, is studied. Furthermore, datapath based on the pseudo asynchronous concept is designed.In pseudo asynchronous datapath, data flow in pipeline is controlled by a completion signal. However, due to the generation delay of completion detection in previous design, the overall speed was limited. n our research, to generate the completion signal as fast as the alculation speed, completion prediction method is proposed. As a case tudy, the completion prediction method is applied to both ripple carry adder (RCA) and carry lookahead adder (CLA). Circuit simulation results show that speed improvement is 20% to 66% in average case compared with corresponding conventional synchronous adders. Such a kind of adder is designed to be implemented as LSI IP (Intellectual Property) without much effort.We have been performing research work on low power LSI design by means of data encoding on inter/intra-chip bus interface. However, when we apply this method to a synchronous system, the data transfer delay problem due to the encoding has to be solved. In asynchronous or pseudo asynchronous system, which is constructed with blocks that don't have constant delay, the delay time generated in bus interface is not critical.In this year, we concentrate our research focus on data encoding without redundant bit, which allows least changes on bus interface except for the driver circuits. With statistical calculations on data transfer, encoding codebook is updated in real time. As a result, although redundant bit is not used, up to 20% signal transitions in bus are cut off.