Integrated Circuit with Semantic Checking Mechanism

具有语义检查机制的集成电路

• 批准号: 02650258
• 负责人: ASADA Kunihiro
• 金额: $ 1.22万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for General Scientific Research (C)
• 财政年份: 1990
• 资助国家: 日本
• 起止时间: 1990 至 1991
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-02650258/
• 关键词: Fault forerant VLSI; Redundant circuit; Fault self-checking; Hardware semantic checking

As the first step in order to develop a semantic checking mechanism in integrated circuits, case study has been carried out for a VLSI control system ; an inverted pendulum control system. Here, in addition to the well known control algorithm for upstanding, several heuristic rules were introduced to avoid unreasonable control signal generation such like a signal toward disturbing stable upstanding. These rules have been tested using a fault simulator, which has been developed specifically to this studv on work station. Through the evaluation by simulation, heuristic rules have been scored from a view point of effectivity for hitting(or detecting)faulty situation. After iterating these heuristic rule introduction and screening by fault simulation, a few effective rules has been obtained, which can keep the inverted pendulum upstanding, even in the frequent intermittent fault. Next, the above mentioned rule based semantic checking mechanism has been evaluated in terms of hardware overhead ; cost, by actually designing controller in a register transfer level description. Here, two approaches were compared ; (1)separate implementation where normal controller element circuits and semantic checking circuits are mutually separated, and(2)merged implementation where normal element circuits and semantic checking circuits are realized as common hardware circuits. Apparently the approach(1)is more effective for this purpose but the research results showed that the approach(2)is also effective under intermittent fault condition. The hardware overhead depends on the rule set and from about 20 Based on the case study a systematic methodology toward designing VLSI's with semantic checking mechanism has been established, although some part in the methodology is still heuristic. As a conclusion, the effectiveness and reality of VLSI's with semantic checking mechanism have been confirmed through this study, which will contribute to the future ultra-reliable VLSI systems.

作为开发集成电路语义检查机制的第一步，对VLSI控制系统进行了案例研究；倒立摆控制系统。这里，除了众所周知的直立控制算法之外，还引入了几种启发式规则以避免不合理的控制信号生成，例如干扰稳定直立的信号。这些规则已经使用故障模拟器进行了测试，该模拟器是专门为此工作站上的该研究开发的。通过模拟评估，从命中（或检测）故障情况的有效性角度对启发式规则进行了评分。经过对这些启发式规则的迭代引入和故障模拟的筛选，得到了一些有效的规则，即使在频繁的间歇性故障中也能保持倒立摆的直立。接下来，从硬件开销方面对上述基于规则的语义检查机制进行了评估；成本，通过在寄存器传输级描述中实际设计控制器来实现。在这里，比较了两种方法； (1)单独实现，其中正常控制器元件电路和语义检查电路相互分离，以及(2)合并实现，其中正常元件电路和语义检查电路被实现为公共硬件电路。显然，方法（1）对于此目的更有效，但研究结果表明，方法（2）在间歇性故障条件下也有效。硬件开销取决于规则集，并且基于大约 20 个案例研究，已经建立了一种设计具有语义检查机制的 VLSI 的系统方法，尽管该方法中的某些部分仍然是启发式的。总之，本研究证实了具有语义检查机制的VLSI的有效性和现实性，这将为未来超可靠的VLSI系统做出贡献。

项目成果

Kunio Nakaguro: "A Design Method of Pseudo-Self-Checking LSI System Using Cascode Voltage Switch Logic" The Transactions of The Institute of Electronics, Information and Communication Engineers. E73. 1973-1978 (1990)

Kunio Nakaguro：“一种使用共源共栅电压开关逻辑的伪自检LSI系统的设计方法”电子信息与通信工程师学会汇刊。

中畔 邦雄: "A Design Method of PseudoーSelfーChecking LSI System Using Cascode Voltage Switch Logic" The Transaction of The Institute of Electronics,Information and Communication Engineers. E73. 1973-1978 (1990)

Kunio Nakawa：“使用共源共栅电压开关逻辑的伪自检 LSI 系统的设计方法”电子、信息和通信工程师学会会刊 E73（1990 年）。