Investigation of high performance three-dimensional integrated circuits using three dimensional MOS devices

使用三维MOS器件的高性能三维集成电路的研究

• 批准号: 10555112
• 负责人: ENDOH Tetsuo
• 金额: $ 8.13万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1998
• 资助国家: 日本
• 起止时间: 1998 至 1999
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10555112/
• 关键词: MOS transistor; Three dimensional MOS transistor; SGT; Three dimensional integrated circuit; 3次元MOSFET

(1) Design and fabrication of SGT-type three-dimensional MOS transistor and its basic circuits.The design system for the elementary three-dimensional transistor and three dimensional circuit were set-up and calibrated. The process flow to make the designed SGT type three dimensional MOS transistor and the elementary three-dimensional circuits were established.(2) Clarifying the specific design parameters for the three-dimensional integrated circuit.Evaluation system for three dimensional integrated circuit was constructed. By using this system, the SGT type three-dimensional MOS transistor and the elemental three dimensional circuit were evaluated. As a result of this evaluation, the specific design parameters for three-dimensional circuit was clarified.(3) Proposal of a high packing density three dimensional memoryThe Stacked Surrounding Gate Transistor (S-SGT)DRAM is proposed as a high packing density three-dimensional memory structure, according to the design rule for proposed three dimensional integrated circuit. This memory was structured by stacking several SGT-type cells in series vertically. S-SGT DRAM was realized by new three-dimensional stacking memory array technologies. It was clarified that the S-SGT DRAM which had the 4 stacking cells can achieve the cell size of 1.44FィイD12ィエD1 where the conventional DRAM can realize the 12FィイD12ィエD1.(4) Design investigation of a high packing density three dimensional memoryS-SGT DRAM process design was proposed and a cell size of 2.4FィイD12ィエD1 was realized.(5) SummaryIn summary, the above given investigations resulted in a systematic, clarification of the basic design rule of SGT and of the corresponding three-dimensional integrated circuit architecture.

(1)SGT型三维MOS晶体管及其基本电路的设计与制作，建立了三维晶体管和三维电路的基本设计系统，并进行了标定。建立了所设计的SGT型三维MOS晶体管的制作工艺流程和基本的三维电路。(2)明确了三维集成电路的具体设计参数，构建了三维集成电路的评价体系。利用该系统对SGT型三维MOS晶体管和基本三维电路进行了评价。作为评估的结果，明确了三维电路的具体设计参数。(3)一种高封装密度三维存储器的提出根据三维集成电路的设计原则，提出了一种高封装密度三维存储器结构--叠层环绕栅晶体管（S-SGT）DRAM。该存储器由垂直串联堆叠的几个SGT型单元构成。S-SGT DRAM是通过新的三维堆叠存储器阵列技术实现的。已经阐明，具有4个堆叠单元的S-SGT DRAM可以实现1.44F堆叠D12堆叠D1的单元尺寸，而传统DRAM可以实现12 F堆叠D12堆叠D1。(4)提出了一种高封装密度三维存储器S-SGT DRAM工艺设计研究，并实现了2.4F的存储单元尺寸D12-D12。(5)总结总之，上述调查导致了SGT和相应的三维集成电路架构的基本设计规则的系统化、澄清。

项目成果

鈴木 正彦: "Stacked-SGT DRAM を用いた2.4F^2メモリセル技術"電子情報通信学会論文誌 C(C-I,C-II合併号). J83-C No.1. 92-93 (2000)

Masahiko Suzuki：“使用 Stacked-SGT DRAM 的 2.4F^2 存储单元技术”，电子、信息和通信工程师协会学报 C（C-I、C-II 合并期）第 1 期（J83-C 第 1 期）。 2000)

Masahiko Suzuki: "The 2.4FィイD12ィエD1 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM"The transactions of the institute of electronics, information and communication engineers. J83-C, No.1, (C-I, C-II combined issue). 92-93 (200

Masahiko Suzuki：“采用堆叠式环绕栅极晶体管 (S-SGT) DRAM 的 2.4F D12D1 存储单元技术”电子、信息和通信工程师研究所的交易 J83-C，No.1，（C-I、C-）。 II 合并问题）92-93（200）。

鈴木正彦: "Stacked-SGT DRAMを用いた2.4F^2メモリセル技術"電子情報通信学会論文誌C(C-I,C-I I合併号). J83-C No.1. 92-93 (2000)

Masahiko Suzuki：“使用 Stacked-SGT DRAM 的 2.4F^2 存储单元技术”，电子、信息和通信工程师协会 C 刊（C-I、C-I I 合刊）（J83-C No.1）。 2000)

遠藤 哲郎: "3次元階層メモリアレイー技術を用いたStacked-SGT DRAM" 電子情報通信学会論文誌C-II. J81-C-I・No.5. 288-289 (1998)

Tetsuro Endo：“使用三维分层存储器阵列技术的 Stacked-SGT DRAM” IEICE Transactions C-II，No. 5. 288-289 (1998)

Tetsuo ENDOH: "The Analysis of the Stacked-Surrounding Gate Transistor(S-SGT)DRAM for the High Speed and Low Voltage Operation" IEICE TRANSACTIONS ON ELECTRONICS. E81-C・No.9. 1491-1498 (1998)

Tetsuo ENDOH：“用于高速和低电压操作的堆叠式环绕栅极晶体管（S-SGT）DRAM 的分析”IEICE TRANSACTIONS ON ELECTRONICS E81-C·No.9（1998）。