Design for Fault Tolerant VLSI Chips

本课题的研究目标是为通用型超大规模集成电路（VLSI）芯片开发十年后可使用的提高芯片成品率和正常运行时芯片容错的技术。这些技术在体系结构设计、逻辑设计和电路设计中得到了发展。我们得到了以下结果。(1)缺陷和故障的重构方法对于FPGA芯片的缺陷和容错重构，我们得到了以下3个结果。（1.1）针对CLB （Configuration Logic Block）缺陷和故障的重构设计；（1.2）针对布线区缺陷和故障的重构设计；（1.3）针对SRAM缺陷和故障的诊断和重构设计。(2)易于测试的逻辑设计我们得到了以下3个结果。（2.1）使用状态转移图连接测试向量生成时序电路短测试序列；（2.2）部分扫描FF的FF选择方法；研究复位FF与故障覆盖率的关系；以及使用检查点的BIST (Built-In Self-Test);（2.3）高速测试的FPGA设计与测试生成。(3)便于错误恢复的架构设计我们得到了以下4个结果。（3.1） LPU-MPU- hpu三级分层并行处理系统的LPU-MPU架构设计；（3.2）并行处理系统中错误恢复的检查点方法；（3.3）高可靠模式和正常模式的多模式系统设计；（3.4）节点或链路故障并行系统的路由算法。

The target of this research was to develop the techniques making chip yield increase for fabrication and making chip fault tolerance during notmal operation for general purpose VLSI chip which would be used after ten years. The technieques were developed in the architecture design, logical design, and circuit design. We have got the following results.(1) Reconfiguration method for defects and faultsWe have got the following 3 resuts for defect and fault tolerance in reconfiguring FPGA chips. (1.1) Reconfiguration designs against defects and faults in CLB (Configuration Logic Block), (1.2) Reconfiguration designs against defects and faults in wiring area, and (1.3) Diagnosis and Reconfiguration designs against defects and faults in SRAM.(2) Easily testable logic designWe have got the following 3 resuts. (2.1) Short test sequence generation for sequential circuits by connecting test vectors using a state transition diagram, (2.2) FF selection method for partial scan FFs, A study for the relation between reset FFs and fault coverage, and BIST (Built-In Self-Test) using check points, and (2.3) FPGA design and test generation for the high speed testing.(3) Architecure design for easy error recoveryWe have got the following 4 resuts. (3.1) LPU-MPU architecture design for LPU-MPU-HPU, 3-lebel hierarchical, parallel processing system, (3.2) Checkpointing method for error recovery in parallel processing systems, (3.3) Multiple mode system design with high reliable mode and normal modes, and (3.4) Routing algorithms for parallel systems with faults in nodes or links.