权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Design for Fault-Tolerant Programmable Chips

容错可编程芯片的设计

基本信息

批准号：
13650370
负责人：
ITO Hideo
金额：
$ 2.05万
依托单位：
Chiba University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2003
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13650370/
关键词：
FPGA Programmable Chip Defect Defect Tolerance Fault Detection Reconfiguration Error Recovery マルチコンテキスト SOC カバリッジ

项目摘要

We have got the following results concerning (1),(2),(3),and (4).(1)Defect Tolerant DesignWe proposed a defect and fault tolerant design for SOC, which is built by cores having the heterogenieous structutures. We proved the efficiency of our design by numerical evaluation results. We also proposed a defect and fault tolerant design for SOC consisting of cores which arc built in hierachical manner and where the lowest level circuits have homogenious structures. We applied our strategy to 32-bits parallel multiplier to show the efficiency of our design.(2)FPGA TestingA test method for mufti-context FPGA has been proposed. This method has the advantage of having small number of writing times for configuration memory. In this context, survey for conventional works about FPGA testing, defect and fault tolerant designs have been made.(3)VISI TestingWe have investigated the following directions of research in testing: a design for BISTs for delay fault detection and analysis of delay fault detection, two test methods using programmable cores in SOC for testing circuits under the test, and design of BIST for SOC which are made in hierarchical structure.(4)Architecture for Fault Tolerance and RecoveringWe proposed an easily recovering method from deadlock in an interconnection network We evaluated the performance by the analysis of the network In this area of research fault tolerant routing in an interconnection network and fault tolerant wormhole-based switching making possible backtracking have been proposed.

关于（1）、（2）、（3）和（4）我们得到了下列结果。（1）容错设计提出了一种基于异构核的SOC容错设计方法。我们证明了我们的设计的效率，数值评估结果。我们也提出了一个缺陷和容错设计的SOC组成的核心，弧建立在分层的方式和最低级别的电路具有同质结构。最后将该策略应用于32位并行乘法器的设计中，验证了该设计的有效性。（2）FPGA测试提出了一种多上下文FPGA的测试方法。该方法具有对配置存储器的写入次数少的优点。在此背景下，对FPGA测试、缺陷和容错设计的传统工作进行了综述。（3）VISI测试研究了以下几个方面的测试研究方向：用于延迟故障检测的BIST设计和延迟故障检测的分析，两种利用SOC中可编程核对被测电路进行测试的方法，以及分层结构SOC的BIST设计。（4）容错和恢复体系结构我们提出了一种轻松从互连网络中的死锁中恢复的方法我们通过对网络的分析来评估性能在该研究领域，互连网络中的容错路由和基于虫洞的容错交换使得回溯成为可能。