Design for Fault-Tolerant Programmable Chips

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We have got the following results concerning (1),(2),(3),and (4).(1)Defect Tolerant DesignWe proposed a defect and fault tolerant design for SOC, which is built by cores having the heterogenieous structutures. We proved the efficiency of our design by numerical evaluation results. We also proposed a defect and fault tolerant design for SOC consisting of cores which arc built in hierachical manner and where the lowest level circuits have homogenious structures. We applied our strategy to 32-bits parallel multiplier to show the efficiency of our design.(2)FPGA TestingA test method for mufti-context FPGA has been proposed. This method has the advantage of having small number of writing times for configuration memory. In this context, survey for conventional works about FPGA testing, defect and fault tolerant designs have been made.(3)VISI TestingWe have investigated the following directions of research in testing: a design for BISTs for delay fault detection and analysis of delay fault detection, two test methods using programmable cores in SOC for testing circuits under the test, and design of BIST for SOC which are made in hierarchical structure.(4)Architecture for Fault Tolerance and RecoveringWe proposed an easily recovering method from deadlock in an interconnection network We evaluated the performance by the analysis of the network In this area of research fault tolerant routing in an interconnection network and fault tolerant wormhole-based switching making possible backtracking have been proposed.