A Study of a High-Speed and Highly-Functional Instruction Feeding Mechanism for the VLSI Architecture

VLIW体系结构是下一代微处理器最有希望实现的体系结构，它并行执行多条指令，需要高性能的存储器系统在短时间内从主存向其功能单元提供大量指令。我们介绍了一种高性能的指令高速缓存机制，专门用于VLIW架构，命名为MULHI（MULtiple HIT）高速缓存。MULHI高速缓存通过从其高速缓存存储器阵列中消除不必要的“nop”指令来实现高高速缓存命中率，从而能够创建高带宽存储器系统。MULHI高速缓存基于与COMPRESS高速缓存和筒仓高速缓存相同的概念，从数据阵列中消除nop。然而，只有MULHI Cache可以将Cache关联性应用到其Cache管理策略中以获得更高的Cache命中率。通过软件模拟，我们评估了MULHI Cache的未命中率，表明它比其他Cache机制获得了更高的OPC操作周期。此外，我们还进行了详细的硬件设计，表明MULHI缓存控制逻辑电路的开销是非常小的。最后，作为高速缓存的一个新应用，我们对一个实时光线跟踪系统进行了评估，该系统在绘制图像方面具有非常强大的功能。

The VLIW architecture, that is the most promising for the implementation of the next generation microprocessors, executes many instructions in parallel, requiring a high performance memory system to supply a huge number of instructions in short time from the main memory to its functional units. We introduce a high performance instruction cache mechanism devoted to the VLIW architecture, named the MULHI (MULtiple HIt) cache. A MULHI cache achieves high cache hit ratio by eliminating unnecessary "nop" instructions from its cache memory array, that enables to create a high-bandwidth memory system.The MULHI cache is based on the same concept with the COMPRESS cache and the SILO cache, at the point of eliminating nops from their data array. However, only the MULHI cache could apply a cache associativity to its cache management policy to acquire a higher cache hit ratio.Using software simulations, we evaluate the MULHI cache miss ratio that show it achieve a higher (OPC Operations Per Cycle) than the other cache mechanisms. Moreover, we make a detailed hardware design, that show the overhead of the MULHI cache control logic circuits is significantly small. Consequently, the MULHI cache architecture is much feasible for implementing a high speed memory system for VLIW processors.At last, as a new application of cache memory, we evaluate a real-time ray tracing system, that is remarkably powerful for rendering images.