SGER: A VLIW/Superscalar Heterogeneous Multi-core Architecture and the Compiler Support

SGER：VLIW/超标量异构多核架构和编译器支持

• 批准号: 0613244
• 负责人: Wei Zhang
• 金额: --
• 依托单位: Southern Illinois University at Carbondale
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-02-15 至 2007-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0613244&HistoricalAwards=false
• 关键词: SGER; VLIW; Superscalar; Heterogeneous; Multi

Intellectual MeritThis research will help to address the challenging and pressing issueof designing compiler-friendly multi-core architectures and developing effective compilersupport for automatically parallelizing single-threaded programs to fully utilize thepotential of multi-core processors. This research will also increase our understanding ofthe interactions between VLIW core(s) and superscalar core(s) on a single chip forcollaboratively exploiting multi-grained parallelisms with different behaviors. Thedeveloped simulator/compiler framework will also be made publicly available, which canfacilitate a number of stimulating follow-on researches, such as energy efficiencyevaluation of the hybrid multi-core, or studying the integration of the hybrid compiler andO.S in multi-programming environments, etc.Broader ImpactThe success of this project will open the door to a number of possiblefollow-on research projects to create practical hybrid multi-core processors and therelated software systems, which will smoothen and accelerate the transition to the multicoreprocessor-based systems and thus greatly benefit the microprocessor industry, as thesingle-thread performance can be continuously improved without fundamentallychanging the programming paradigm. The proposed hybrid multi-core architecture canalso be potentially customized for a great variety of embedded applications that demandboth high performance and energy efficiency. Moreover, since future high-performancecomputing systems are very likely to utilize the multi-core processors as the basic nodes,the transparent single-thread performance enhancement achieved by this project will alsohelp to advance the power of computing into the next generation for meeting the toughestcomputational challenges. Additionally, this project will attract and train graduatestudents in multi-core architecture and advanced compiler design, and the research resultswill also be incorporated into the graduate level computer architecture course, i.e., ECE532, to better prepare the students for this rapidly developing field.

本研究将有助于解决设计编译器友好的多核架构和开发有效的编译器支持自动并行单线程程序的挑战和紧迫问题，以充分利用多核处理器的潜力。这项研究还将增加我们对单芯片上VLIW核和超标量核之间相互作用的理解，以协同开发具有不同行为的多粒度并行性。开发的模拟器/编译器框架也将公开提供，这可以促进一些刺激的后续研究，如混合多核的能源效率评估，或研究混合编译器和do的集成。更广泛的影响这个项目的成功将为一些可能的后续研究项目打开大门，以创建实用的混合多核处理器和相关的软件系统，这将平滑和加速向基于多核处理器的系统的过渡，从而极大地有利于微处理器行业，因为这些单线程性能可以不断提高，而不会从根本上改变编程范式。所提出的混合多核架构还可以针对各种要求高性能和高能效的嵌入式应用进行定制。此外，由于未来的高性能计算系统很可能利用多核处理器作为基本节点，本项目实现的透明单线程性能增强也将有助于将计算能力提升到下一代，以应对最严峻的计算挑战。此外，本项目将吸引和培养多核体系结构和高级编译器设计方面的研究生，研究成果也将纳入研究生阶段的计算机体系结构课程，即ECE532，为学生更好地为这一快速发展的领域做好准备。