Hardware Synthesis of High-speed Network Monitors

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Due to recent progress of the Internet, We need high-speed network monitors which can observe millions of packets per second. This research proposes a technique to synthesize hardware circuits from formal specifications of high-Speed network monitors described in LOTOS language.In the proposed method, a given network monitor is modeled as concurrent EFSMs, and data exchange among them is specified using multi-rendezvous in LOTOS. Depending on monitoring items and network speeds,We must derive different hardware circuits. For such parameter values, the proposed method can automatically select suitable hardware modules and adjust parameter values of the derived hardware component. We have developed a tool to generate the corresponding RT-level VHDL Specification from a given specification, and synthesize an FPGA circuit from the derived VHDL description. From our experiments, We have confirmed that the generated circuits have enough speeds for monitoring packets in Gigabit Ethernet.