Research on HW/SW Co-design of Network Systems with Timing Constraints

随着无线局域网、无线码分多址等高速无线网络技术的发展，手机终端集成了网络浏览、高质量音频播放、数码相机、可视电话等新功能。为了实现这种高功能的终端，使用了包括CPU、DSP、存储器和电荷耦合器件在内的各种部件。为了缩短开发周期，节省满足预期性能和时间约束的组件的总成本，我们需要使用通用组件高效地开发实时嵌入式系统的方法。本文提出了一种利用现场可编程门阵列和通用硬件部件设计高可靠实时嵌入式系统的方法。在我们的方法中，我们将系统描述为具有时间约束的并发周期EFSM的并行组合。我们给出了数据处理时间和数据输入/输出时间等性能值作为EFSM中转换条件的参数。利用参数模型检验技术，我们导出了一个参数条件C，它必须满足系统规格说明S无死锁地进行并且满足给定的时间约束R。通过准备可用部件的性价比特性列表，并用它们的值替换导出的参数条件C，我们可以自动选择使总成本最小的适当的部件组合。我们已经开发了一个基于该技术的设计支持工具。从系统规格说明出发，我们的综合工具可以得到一个RT级的VHDL语言描述，它可以被综合为一个用于控制部件和在部件之间传输数据的FPGA电路。我们已经将我们的技术应用到手机基本功能的开发中，并证实了它的有效性。

Due to the progress of the high-speed wireless network technologies such as WLAN and WCDMA, many new functions like web browsing, high-quality audio playback, digital camera, and video telephony have been integrated into cellular phone terminals. Various components including CPU,DSP, memory and CCD are used to realize such highly functional terminals. In order to shorten the development period and save the total cost of components satisfying expected performance and timing constraints, we need methods for efficiently developing a real-time embedded system using general components. In this paper, we propose a method for designing high-reliable real-time embedded systems with FPGA and general hardware components. In our method, we specify a system as a parallel composition of concurrent periodic EFSMs with timing constraints. We give performance values like data processing time and data input/output time as parameters of transition conditions in the EFSMs. Using a parametric model checking technique, we derive a parameter condition C which must hold for a system specification S to proceed without deadlocks and satisfy given timing constraints R. By preparing a list of cost-performance characteristics of available components and substituting their values to the derived parameter condition C we can automatically select an appropriate combination of components which minimizes the total cost. We have developed a design support tool based on the proposed technique. From a system specification, our synthesis tool can derive an RT-level VHDL description which can be synthesized as an FPGA circuit for controlling the components and transferring data among them. We have applied our technique to development of a basic functionality of a cellular phone and confirmed its usefulness.