Hardware Synthesis of Communication Protocols in Real-Time LOTOS Language

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This research proposes a concurrent periodic EFSMs model and a technique to synthesize hardware circuits from specifications of real-time systems described in Real-Time LOTOS language. In the proposed model, data exchange by synchronous execution of the same events in multiple EFSMs can be specified as multi-way synchronization in LOTOS.The executable time range of each event can be given as a logical conjunction of linear inequalities of the execution time of its preceding events. Since each EFSM has some branches and some combination of branches of those EFSMs may not be executable because of their timing constraints, the proposed synthesis technique finds only executable combination of branches from a given specification and generates a scheduler for event sequences in each executable combination of branches. We have developed a tool to generate the corresponding RTL-level VHDL specification from a given specification, and generated circuits from some specifications such as a video playback chip. From those experiments, we have confirmed that the performance and size of the generated circuits are reasonable for practical use.