Studies on Test Architecture for Test Data Compression / Decompression

从实用性的角度对VLSI测试数据压缩和解压缩方案进行了研究。2003年，我们首先分析了变长码压缩算法与测试应用之间的关系。在此基础上，提出了一种应用压缩测试数据的带缓冲的解压缩器模型。该模型可能会对测试应用提出一些限制。此外，我们还提出了一种测试向量重新排序算法来最小化解压缩器模型上的缓冲区大小。另一方面，提出了一种基于霍夫曼编码的响应压缩编码方法。2004年，在上述分析的基础上，我们提出了一种新的基于霍夫曼编码方法，在给定的测试环境下实现了较小的测试应用时间。所提出的编码方法根据测试环境对索字的压缩比和长度进行调整。我们还提出了一种经济有效的测试生成方法，用于高度可压缩的测试数据，同时保持生成的测试集数量较少。此外，我们还开始讨论可重构VLSI解压缩器的灵活性。2005年，我们发展了去年的讨论，并引入了一种可根据所用编码算法和给定测试数据进行重构的嵌入式解压缩器。它的可重构性可以在保持高压缩比的前提下克服传统解压缩器的缺点。此外，我们还提出了一种适用于四种可变长度编码的可重构解压缩器结构。在该体系结构中，四种编码的公共功能被实现为固定的(或不可重构的)组件，以减少存储在ATE上并发送到CUT的配置数据。

We researched test data compression and decompression schemes for VLSI testing in terms of usefulness.In 2003, first, we analyzed a relationship between compression algorithms using variable-length codes and test application. Based on this analysis, we proposed a model of decompressors with buffer for applying compressed test data. This model can raise some limitations on test application. In addition, we proposed a test vector reordering algorithm to minimize the size of the buffer on the decompressor model. On the other hand, we proposed a response compression coding method based on Huffman coding. The proposed coding method guarantees zero-aliasing and it is independent of the fault model and the structure of a circuit-under-test.In 2004, according to the above analysis, we proposed a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the length of the cord words to the test environment. We also proposed a cost-effective test generation method for highly compressible test data while keeping the number of generated test sets small. Moreover, we began to discuss flexibility of decompressors using reconfigurable VLSI.In 2005, we developed the last year's discussion, and introduced an embedded decompressor that is reconfigurable according to the used coding algorithms and a given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-reconfigurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT.