A research of low-voltage analog circuit techniques in the 90 nm CMOS era

1. 2006年，我们获得了一个原型ADC芯片，采用90 nm CMOS工艺制造。制造运行由VDEC（Tbkyo大学）支持。该ADC芯片采用12位流水线结构，采用电流模式电路技术设计。评估的性能为2 V工作电压、25 MS/s速度、48 dB信噪比和8位精度。低电压工作是可以的，但留下的问题是精度和速度。2.性能适中，但电路技术是优秀的，未来有可能实现更高性能的ADC。该ADC的论文被IEEE CICC接受，并于2007年9月在旧金山弗朗西斯科发表。然而，为了在100 MHz的时钟速度下实现10位精度，还需要进一步的研究。深入分析了原型ADC无法实现目标的原因之一是时钟驱动器部分。端接电阻的使用是最好的，使ADC的工作速度比原型ADC快得多。另一个原因是设计错误，在时序控制的子DAC的一个位块。由于这一点，电流镜晶体管的栅极电压在前一阶段中的电流变化的转变上变得无效。2007年使用SPICE电路仿真程序对电路进行了修改和仿真，虽然是仿真基础，但已观察到线性度提高了5倍。我们在2007年秋天重新开始了电路设计。虽然我们还没有达到重新设计的ADC的布局阶段，我们希望在2008年有第二个版本的ADC芯片。我们希望有10位的精度和更快的转换速度比以前。

1. In 2006, we obtained a prototype ADC chip which was fabricated by using 90 nm CMOS process. The fabrication run was supported by VDEC (University of Tbkyo). The ADC chip was in the 12-bit pipelined configuration that has been designed by using current-mode circuit techniques. The evaluated performances were a 2 V operation, a 25 MS/s speed, a 48 dB of Signal-to-Noise ratio, and an 8-bit accuracy. Low-voltage operation was OK, however, problems left are accuracy and speed.2.The performance was moderate, however, the circuit technique was excellent and the future possibility to realize more high performance ADC was seen. The paper of this ADC was accepted to IEEE CICC and was presented in San Francisco in September, 2007.3. Still, further study is necessary for realizing 10-bit accuracy with the clock speed of 100 MHz. Analyses have intensively done to find what were wrong for the prototype ADC not to be able to achieve the goalOne reason was in the clock driver part. The use of the termination resistor is preferable to make the ADC operate much faster than the prototype ADC.The other reason was the design mistake in timing control of the sub-DAC iti a bit-block. Due to this, the gate voltage of current-mirror transistors became inactive on the transition of current change in the previous stage.4. The circuit has been modified and simulated by using SPICE circuit simulation program in 2007, and 5 times of the improvement of linearity has been observed although it is the simulation basis. We started the circuit design again in the fall of 2007. Although we have not reached the layout stage of the re-designed ADC, we would like to have the 2nd version of ADC chip in 2008. We expect to have 10-bit accuracy and faster conversion rate than before.