A research of low-voltage analog circuit techniques in the 90 nm CMOS era

90 nm CMOS时代低压模拟电路技术研究

基本信息

  • 批准号:
    18560346
  • 负责人:
  • 金额:
    $ 2.4万
  • 依托单位:
  • 依托单位国家:
    日本
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
  • 财政年份:
    2006
  • 资助国家:
    日本
  • 起止时间:
    2006 至 2007
  • 项目状态:
    已结题

项目摘要

1. In 2006, we obtained a prototype ADC chip which was fabricated by using 90 nm CMOS process. The fabrication run was supported by VDEC (University of Tbkyo). The ADC chip was in the 12-bit pipelined configuration that has been designed by using current-mode circuit techniques. The evaluated performances were a 2 V operation, a 25 MS/s speed, a 48 dB of Signal-to-Noise ratio, and an 8-bit accuracy. Low-voltage operation was OK, however, problems left are accuracy and speed.2.The performance was moderate, however, the circuit technique was excellent and the future possibility to realize more high performance ADC was seen. The paper of this ADC was accepted to IEEE CICC and was presented in San Francisco in September, 2007.3. Still, further study is necessary for realizing 10-bit accuracy with the clock speed of 100 MHz. Analyses have intensively done to find what were wrong for the prototype ADC not to be able to achieve the goalOne reason was in the clock driver part. The use of the termination resistor is preferable to make the ADC operate much faster than the prototype ADC.The other reason was the design mistake in timing control of the sub-DAC iti a bit-block. Due to this, the gate voltage of current-mirror transistors became inactive on the transition of current change in the previous stage.4. The circuit has been modified and simulated by using SPICE circuit simulation program in 2007, and 5 times of the improvement of linearity has been observed although it is the simulation basis. We started the circuit design again in the fall of 2007. Although we have not reached the layout stage of the re-designed ADC, we would like to have the 2nd version of ADC chip in 2008. We expect to have 10-bit accuracy and faster conversion rate than before.
1. 2006年,我们获得了一个原型ADC芯片,采用90 nm CMOS工艺制造。制造运行由VDEC(Tbkyo大学)支持。该ADC芯片采用12位流水线结构,采用电流模式电路技术设计。评估的性能为2 V工作电压、25 MS/s速度、48 dB信噪比和8位精度。低电压工作是可以的,但留下的问题是精度和速度。2.性能适中,但电路技术是优秀的,未来有可能实现更高性能的ADC。该ADC的论文被IEEE CICC接受,并于2007年9月在旧金山弗朗西斯科发表。然而,为了在100 MHz的时钟速度下实现10位精度,还需要进一步的研究。深入分析了原型ADC无法实现目标的原因之一是时钟驱动器部分。端接电阻的使用是最好的,使ADC的工作速度比原型ADC快得多。另一个原因是设计错误,在时序控制的子DAC的一个位块。因此,电流镜晶体管的栅极电压在前一阶段电流变化的转变时变得无效。4.该电路在2007年进行了修改和SPICE电路仿真程序的仿真,并已观察到5倍的线性度的改善,虽然它是仿真的基础。我们在2007年秋天重新开始了电路设计。虽然我们还没有达到重新设计的ADC的布局阶段,我们希望在2008年有第二个版本的ADC芯片。我们希望有10位的精度和更快的转换速度比以前。

项目成果

期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture
具有 1.5 位位块架构的 CMOS 流水线 ADC 的数字辅助增益和偏移误差消除技术
A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain
一种电流模式 ADC,通过在数字域中切换电流和计算数据来实现电流交换和平均功能
  • DOI:
  • 发表时间:
    2007
  • 期刊:
  • 影响因子:
    0
  • 作者:
    N.Yoshii;K.Mizutani and Y.Sugimoto
  • 通讯作者:
    K.Mizutani and Y.Sugimoto
「研究成果報告書概要(和文)」より
摘自《研究结果报告摘要(日文)》
  • DOI:
  • 发表时间:
    2005
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Kawauchi;et. al.;Nishimura et al.;Dezawa et al.;Yoshizawa et al.;星野 幹雄;星野 幹雄
  • 通讯作者:
    星野 幹雄
A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA
{{ item.title }}
{{ item.translation_title }}
  • DOI:
    {{ item.doi }}
  • 发表时间:
    {{ item.publish_year }}
  • 期刊:
  • 影响因子:
    {{ item.factor }}
  • 作者:
    {{ item.authors }}
  • 通讯作者:
    {{ item.author }}

数据更新时间:{{ journalArticles.updateTime }}

{{ item.title }}
  • 作者:
    {{ item.author }}

数据更新时间:{{ monograph.updateTime }}

{{ item.title }}
  • 作者:
    {{ item.author }}

数据更新时间:{{ sciAawards.updateTime }}

{{ item.title }}
  • 作者:
    {{ item.author }}

数据更新时间:{{ conferencePapers.updateTime }}

{{ item.title }}
  • 作者:
    {{ item.author }}

数据更新时间:{{ patent.updateTime }}

SUGIMOTO Yasuhiro其他文献

Transient response moment analysis of a linear system subjected to non-Gaussian random excitation by the equivalent non-Gaussian excitation method
等效非高斯激励法分析非高斯随机激励线性系统的瞬态响应矩
  • DOI:
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    YOSHIDA Shogo;NAKANISHI Daisuke;NANIWA Keisuke;SUGIMOTO Yasuhiro;OSUKA Koichi;Takahiro Tsuchida and Kohei Kanno
  • 通讯作者:
    Takahiro Tsuchida and Kohei Kanno
Verification of linear approximation model of McKibben Pneumatic Actuator
McKibben气动执行器线性近似模型的验证
  • DOI:
    10.1299/transjsme.18-00498
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    YOSHIDA Shogo;NAKANISHI Daisuke;NANIWA Keisuke;SUGIMOTO Yasuhiro;OSUKA Koichi
  • 通讯作者:
    OSUKA Koichi

SUGIMOTO Yasuhiro的其他文献

{{ item.title }}
{{ item.translation_title }}
  • DOI:
    {{ item.doi }}
  • 发表时间:
    {{ item.publish_year }}
  • 期刊:
  • 影响因子:
    {{ item.factor }}
  • 作者:
    {{ item.authors }}
  • 通讯作者:
    {{ item.author }}

{{ truncateString('SUGIMOTO Yasuhiro', 18)}}的其他基金

Realization of 2-phase CO2 cooling system applicable to advanced detectors
实现适用于先进探测器的两相CO2冷却系统
  • 批准号:
    16H03992
  • 财政年份:
    2016
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Development of a cooling system using 2-phase CO2 for advanced detectors
为先进探测器开发使用两相 CO2 的冷却系统
  • 批准号:
    24540312
  • 财政年份:
    2012
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
Fundamental study on ureterolith formation in ureter stent
输尿管支架内输尿管结石形成的基础研究
  • 批准号:
    24560211
  • 财政年份:
    2012
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
Fundamental study on flow pattern in ureter and ureter stent
输尿管血流模式及输尿管支架的基础研究
  • 批准号:
    22760137
  • 财政年份:
    2010
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Young Scientists (B)
A research to realize a low-voltage analog circuit with a wide signal dynamic range by utilizing the positive feedback
利用正反馈实现宽信号动态范围低压模拟电路的研究
  • 批准号:
    21560363
  • 财政年份:
    2009
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
Motion analysis and application of Passive Dynamic Walking
被动动态行走的运动分析及应用
  • 批准号:
    18760167
  • 财政年份:
    2006
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Young Scientists (B)
Research for the development of the vertex detector using fully-depleted fine-pixel CCD
全耗尽型精细像素CCD顶点探测器的研制研究
  • 批准号:
    17540282
  • 财政年份:
    2005
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
Development of bio-resource recycling agricultural system, and water cleanin system with effective use of digestive fluids from biogas-plant.
开发生物资源循环农业系统和有效利用沼气厂消化液的水净化系统。
  • 批准号:
    16380223
  • 财政年份:
    2004
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Studies on the function and role of grazing domestic animals in the semi-mountainous regions of Kyushu
九州半山区放牧家畜的功能和作用研究
  • 批准号:
    13460120
  • 财政年份:
    2001
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Nitrata pollution of groundwater arising from agricultural practices, and some technologies to conrol the polluion
农业生产引起的地下水硝酸盐污染以及控制污染的一些技术
  • 批准号:
    07458140
  • 财政年份:
    1995
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)

相似海外基金

Microscale enabled advanced flow and heat transfer technologies featuring high performance and low power consumption; Acronym: Micro-FloTec
微尺度实现了高性能、低功耗的先进流动和传热技术;
  • 批准号:
    EP/Y004973/1
  • 财政年份:
    2023
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Research Grant
Development of Low Power Consumption Multiferroic Memory using Experimental and Computational Approaches
使用实验和计算方法开发低功耗多铁存储器
  • 批准号:
    23KJ0919
  • 财政年份:
    2023
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for JSPS Fellows
Micro-FloTec: Microscale enabled advanced flow and heat transfer technologies featuring high performance and low power consumption
Micro-FloTec:Microscale 支持先进的流动和传热技术,具有高性能和低功耗的特点
  • 批准号:
    EP/X038319/1
  • 财政年份:
    2023
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Research Grant
Research and Development of Ultra-Low Power Consumption IoT Systems
超低功耗物联网系统研发
  • 批准号:
    23K11063
  • 财政年份:
    2023
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
Next-generation memory analysis and evaluation technology using statistical electrical measurement with ultra-low power consumption, short processing time, and low cost
采用统计电学测量的下一代内存分析评估技术,具有超低功耗、处理时间短、成本低的特点
  • 批准号:
    23K13372
  • 财政年份:
    2023
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Early-Career Scientists
Development and proof of a 4 K cryocooler that achieves both low power consumption and high efficiency
实现低功耗和高效率的 4K 制冷机的开发和验证
  • 批准号:
    22K04058
  • 财政年份:
    2022
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
Integration of 2 dimensional tunnel FET for ultra-low power consumption system
集成二维隧道 FET,实现超低功耗系统
  • 批准号:
    22H04957
  • 财政年份:
    2022
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (S)
Development of flying object detection system by detecting sound sources of compact, lightweight and low power consumption
开发紧凑、轻量、低功耗的检测声源飞行物体检测系统
  • 批准号:
    22H01434
  • 财政年份:
    2022
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Realizing of non-volatile memory with large capacity and low power consumption by metal-insulator-semiconductor junction composed by phase change material and oxide
利用相变材料和氧化物组成的金属-绝缘体-半导体结实现大容量、低功耗的非易失性存储器
  • 批准号:
    21K20509
  • 财政年份:
    2021
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Research Activity Start-up
Study on a phase-change optical switch for low-power-consumption reconfigurable photonic networks
低功耗可重构光子网络相变光开关研究
  • 批准号:
    21H01398
  • 财政年份:
    2021
  • 资助金额:
    $ 2.4万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
{{ showInfoDetail.title }}

作者:{{ showInfoDetail.author }}

知道了