Floorplan-aware High-level Synthesis

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We propose floorplan-aware high-level synthesis system. This system can synthesize high performance and small area circuit in such situation which interconnect delay is dominate. Propose system decides register/controller architecture configuration and executes scheduling which is appropriate for its configuration based on input application and constraints. Proposed approach can achieve in 10% area reduction compared to state-of-art floorplan-aware high level synthesis system.