Studies on Normal-Operation-Aware Accurate Delay Fault Testing for VLSIs

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Since our life is dependent on computer systems, reliability of the computers is essential. To create reliable systems, very large scale integration circuits (VLSIs), which are the main components of the systems, need to be tested and the test quality must be improved considering their operating environment. Under this grant, for supporting normal-operation-aware testing, a method of test pattern and response delivery using normal operation, a method of thermal-uniformity-aware built-in self-test (BIST), a method of linear feedback shift register (LFSR) seed generation for high quality pseudo-random BIST, and a framework of constrained test generation to generate test and diagnosis patterns with desired properties have been developed.