Dynamic delay fault testing of high-performance digital circuit in deep submicron technology

深亚微米技术下高性能数字电路的动态延迟故障测试

• 批准号: 249639-2007
• 负责人: Sedaghat, Reza
• 金额: $ 1.18万
• 依托单位: Ryerson University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2008
• 资助国家: 加拿大
• 起止时间: 2008-01-01 至 2009-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=394412
• 关键词: Dynamic; delay; fault; testing; performance

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. It has resulted in the design of multi-gigahertz integrated circuit (IC) and unprecedented levels of integration. Modern integrated circuits operate at clock frequencies of more than 3 GHz, and their dies contain close to 300 million transistors. Digital IC performance has followed Moore's law, improving annually by 30%. However, ATE performance has improved by only 12% annually. The discrepancy between ATE edge placement accuracy and circuit under test (CUT) performance1 will make at-speed logic testing increasingly difficult for future deep-submicron technologies (DSM).

在过去的30年里，积极的技术缩放一直是数字CMOS电路设计的支柱。它导致了多千兆赫集成电路（IC）的设计和前所未有的集成水平。现代集成电路的时钟频率超过3 GHz，其芯片包含近3亿个晶体管。数字集成电路的性能遵循摩尔定律，每年以30%的速度提高。然而，ATE性能每年仅提高12%。ATE边缘位置精度和被测电路（CUT）性能之间的差异1将使未来深亚微米技术（DSM）的高速逻辑测试变得越来越困难。