Dynamic delay fault testing of high-performance digital circuit in deep submicron technology

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Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. It has resulted in the design of multi-gigahertz integrated circuit (IC) and unprecedented levels of integration. Modern integrated circuits operate at clock frequencies of more than 3 GHz, and their dies contain close to 300 million transistors. Digital IC performance has followed Moore's law, improving annually by 30%. However, ATE performance has improved by only 12% annually. The discrepancy between ATE edge placement accuracy and circuit under test (CUT) performance1 will make at-speed logic testing increasingly difficult for future deep-submicron technologies (DSM).Most of today's advanced delay faults algorithms are able to propagate those delay faults which are creating logic or glitch faults, but we propose an approaches for gate-delay fault diagnosis in deep sub-micron by a series of injections and evaluations to propagate the actual timing faults as well as those delay faults that eventually creating logic faults to the primary outputs. Unlike the backtrack algorithm that predicts the fault site by tracing the syndrome at a faulty output back into the circuit, this approach propagate the fault from fault site by mapping a nine-valued voltage model on top of a five-valued voltage model. In such a forward approach, the accuracy is much higher because all the composite syndromes at all faulty outputs are considered simultaneously. As a result, the proposed approach is robust and applicable even when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is considerable.