Dynamic delay fault testing of high-performance digital circuit in deep submicron technology

深亚微米技术下高性能数字电路的动态延迟故障测试

• 批准号: 249639-2007
• 负责人: Sedaghat, Reza
• 金额: $ 1.18万
• 依托单位: Ryerson University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2007
• 资助国家: 加拿大
• 起止时间: 2007-01-01 至 2008-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=361223
• 关键词: Dynamic; delay; fault; testing; performance

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. It has resulted in the design of multi-gigahertz integrated circuit (IC) and unprecedented levels of integration. Modern integrated circuits operate at clock frequencies of more than 3 GHz, and their dies contain close to 300 million transistors. Digital IC performance has followed Moore's law, improving annually by 30%. However, ATE performance has improved by only 12% annually. The discrepancy between ATE edge placement accuracy and circuit under test (CUT) performance1 will make at-speed logic testing increasingly difficult for future deep-submicron technologies (DSM).Most of today's advanced delay faults algorithms are able to propagate those delay faults which are creating logic or glitch faults, but we propose an approaches for gate-delay fault diagnosis in deep sub-micron by a series of injections and evaluations to propagate the actual timing faults as well as those delay faults that eventually creating logic faults to the primary outputs. Unlike the backtrack algorithm that predicts the fault site by tracing the syndrome at a faulty output back into the circuit, this approach propagate the fault from fault site by mapping a nine-valued voltage model on top of a five-valued voltage model. In such a forward approach, the accuracy is much higher because all the composite syndromes at all faulty outputs are considered simultaneously. As a result, the proposed approach is robust and applicable even when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is considerable.

在过去的30年里，积极的技术缩放一直是数字CMOS电路设计的支柱。它导致了多千兆赫集成电路（IC）的设计和前所未有的集成水平。现代集成电路的时钟频率超过3 GHz，其芯片包含近3亿个晶体管。数字集成电路的性能遵循摩尔定律，每年以30%的速度提高。然而，ATE性能每年仅提高12%。ATE边缘定位精度和被测电路（CUT）性能之间的差异1将使高速逻辑测试对于未来的深亚微米技术（DSM）变得越来越困难。当今大多数先进的延迟故障算法能够传播那些导致逻辑或毛刺故障的延迟故障，但我们提出了一种方法，门延迟故障诊断深亚，通过一系列的注入和评估来传播实际的定时故障以及最终对初级输出产生逻辑故障的延迟故障。与通过将故障输出处的故障综合征追踪回电路来预测故障部位的回溯算法不同，该方法通过将九值电压模型映射到五值电压模型之上来从故障部位传播故障。在这样的前向方法中，准确度高得多，因为同时考虑了所有故障输出处的所有复合综合征。因此，即使延迟大小相对较小，所提出的方法也是鲁棒且适用的。实验结果表明，该方法产生的故障候选数量是相当可观的。