Equivalence Checking for System-Level Designs Having Different Input-Output Timings

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In this work, design verification methods for embedded systems or VLSIs are studied. The purpose of design verification is to check whether a given design is correct or not and provide failing patterns if incorrect. We focus on equivalence checking of given two designs. Our target of verification is system-level design, which is a highly abstracted design level and has become widely applied recently. We proposed equivalence checking methods that can deal with different input/output timings between given two designs. In addition, we have developed a method to detect potentially equivalent internal variables in designs. The purposed of this work is to improve the ability of equivalence checking for system-level designs by those proposed methods.