Communication analysis for Network-on-Chip

片上网络的通信分析

• 批准号: 5417284
• 负责人: Professor Dr. Oliver Bringmann
• 金额: --
• 依托单位: Fachbereich IV: Informatik
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2004
• 资助国家: 德国
• 起止时间: 2003-12-31 至 2008-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/5417284?language=en
• 关键词: Communication; analysis; Network; Chip

Network-on-Chip (NoC) is a new paradigm to enable an efficient design of future Systems-onChip (SoC), which exploit the multi-billion transistor capacity of single ASICs by composing hundreds of interconnected IP blocks, such as CPU and DSP cores, application specific hardware and large amounts of memory. The major challenge for SoC designers is to master the strongly increased system functionality being accompanied by increasing problems of deep submicron effects (e.g. cross-talk, interference) under timing, area, and low power constraints. Networks-on-Chip are a promising approach to address these problems by replacing global wires and on-chip busses with packet routing networks. The main advantages are reduction of electro-magnetic effects by introducing a well-structured interconnection layout instead of long-distance wiring as well as providing a good scalability and network utilization by using dynamic packet routing instead of on-chip busses and direct networks. The major drawback of on-chip packet-routing architectures is the strongly decreased timing predictability, due to dynamic packet routing, so that NoC architectures are not applicable to a wide bandwidth of embedded real-time applications. Therefore, this project aims to eliminate this problem by investigating new analysis and synthesis methods to determine temporal dependencies for communications, to calculate parameters for automatic network Generation, and to refine analysis methods for NoC communication protocols. Parameter calculation for network Generation include the component placement to minimize communication latencies and conflicts on shared communication resources and the determination of efficient routing at design time in order to guarantee a predictable timing satisfying given timing constraints.

片上网络（Network-on-Chip，NoC）是一种新型的片上系统（Systems-on-Chip，SoC）设计模式，它利用单个ASIC芯片的数十亿晶体管容量，将数百个互连的IP模块（如CPU和DSP内核、专用硬件和大量存储器）组合在一起。SoC设计人员面临的主要挑战是在时序、面积和低功耗限制下，掌握系统功能的大幅增加，同时伴随着越来越多的深亚微米效应问题（例如串扰、干扰）。片上网络是一种很有前途的方法来解决这些问题，通过取代全球线和片上总线与分组路由网络。其主要优点是通过引入结构良好的互连布局而不是长距离布线来减少电磁效应，以及通过使用动态分组路由而不是片上总线和直接网络来提供良好的可扩展性和网络利用率。片上分组路由架构的主要缺点是由于动态分组路由而大大降低了时序可预测性，使得NoC架构不适用于宽带宽的嵌入式实时应用。因此，本项目旨在通过研究新的分析和综合方法来消除这个问题，以确定通信的时间依赖性，计算自动网络生成的参数，并改进NoC通信协议的分析方法。网络生成的参数计算包括元件布局以最小化共享通信资源上的通信延迟和冲突，以及在设计时确定有效路由以保证满足给定时序约束的可预测时序。