Communication analysis for Network-on-Chip

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Network-on-Chip (NoC) is a new paradigm to enable an efficient design of future Systems-onChip (SoC), which exploit the multi-billion transistor capacity of single ASICs by composing hundreds of interconnected IP blocks, such as CPU and DSP cores, application specific hardware and large amounts of memory. The major challenge for SoC designers is to master the strongly increased system functionality being accompanied by increasing problems of deep submicron effects (e.g. cross-talk, interference) under timing, area, and low power constraints. Networks-on-Chip are a promising approach to address these problems by replacing global wires and on-chip busses with packet routing networks. The main advantages are reduction of electro-magnetic effects by introducing a well-structured interconnection layout instead of long-distance wiring as well as providing a good scalability and network utilization by using dynamic packet routing instead of on-chip busses and direct networks. The major drawback of on-chip packet-routing architectures is the strongly decreased timing predictability, due to dynamic packet routing, so that NoC architectures are not applicable to a wide bandwidth of embedded real-time applications. Therefore, this project aims to eliminate this problem by investigating new analysis and synthesis methods to determine temporal dependencies for communications, to calculate parameters for automatic network Generation, and to refine analysis methods for NoC communication protocols. Parameter calculation for network Generation include the component placement to minimize communication latencies and conflicts on shared communication resources and the determination of efficient routing at design time in order to guarantee a predictable timing satisfying given timing constraints.