Communication analysis for Network-on-Chip

片上网络(NoC)是未来片上系统(SoC)的一种新的设计模式，它通过组成数百个互连的IP块，如CPU和DSP内核、专用硬件和大量存储器，来利用单个ASIC的数十亿晶体管容量。SoC设计者面临的主要挑战是掌握在时序、面积和低功耗限制下，伴随着越来越多的深亚微米效应(如串扰、干扰)问题而带来的强大的系统功能。片上网络是解决这些问题的一种很有前途的方法，它用数据包路由网络取代了全局线路和片上总线。其主要优点是通过引入结构良好的互连布局而不是长途布线来减少电磁效应，以及通过使用动态分组路由来代替片上总线和直接网络来提供良好的可扩展性和网络利用率。片上数据包路由体系结构的主要缺点是由于动态数据包路由导致时序可预测性大大降低，因此片上网络体系结构不适用于大带宽的嵌入式实时应用。因此，本项目旨在通过研究新的分析和综合方法来消除这一问题，以确定通信的时间依赖关系，计算用于自动网络生成的参数，并改进NoC通信协议的分析方法。网络生成的参数计算包括元件布局以最小化通信延迟和共享通信资源上的冲突，以及在设计时确定有效的路由以确保可预测的时序满足给定的时序约束。

Network-on-Chip (NoC) is a new paradigm to enable an efficient design of future Systems-onChip (SoC), which exploit the multi-billion transistor capacity of single ASICs by composing hundreds of interconnected IP blocks, such as CPU and DSP cores, application specific hardware and large amounts of memory. The major challenge for SoC designers is to master the strongly increased system functionality being accompanied by increasing problems of deep submicron effects (e.g. cross-talk, interference) under timing, area, and low power constraints. Networks-on-Chip are a promising approach to address these problems by replacing global wires and on-chip busses with packet routing networks. The main advantages are reduction of electro-magnetic effects by introducing a well-structured interconnection layout instead of long-distance wiring as well as providing a good scalability and network utilization by using dynamic packet routing instead of on-chip busses and direct networks. The major drawback of on-chip packet-routing architectures is the strongly decreased timing predictability, due to dynamic packet routing, so that NoC architectures are not applicable to a wide bandwidth of embedded real-time applications. Therefore, this project aims to eliminate this problem by investigating new analysis and synthesis methods to determine temporal dependencies for communications, to calculate parameters for automatic network Generation, and to refine analysis methods for NoC communication protocols. Parameter calculation for network Generation include the component placement to minimize communication latencies and conflicts on shared communication resources and the determination of efficient routing at design time in order to guarantee a predictable timing satisfying given timing constraints.