Ultra-fast H_* controllers using ASIC's and their field development environment

由于软件控制器在高阶情况下速度慢，如H_* 控制，因此有时会结合硬件。大的电路尺寸，特别是由乘法器引起的，会带来问题。该项目的目标是通过减少电路和缩短开发时间来实现速度快100倍的控制器。实际的机制是基于这样一个事实，即控制器中的乘法通常是常数系数：乘法k^* x不被认为有两个输入，而是一个只有x输入的函数f（x）;然后用逻辑综合的方法实现了由x导出f（x）的电路，并对k1^* x1 + k2^* x2 +. kn^* xn通过组合合成常数系数和加法器来实现。通过将长输入字减半并将两个输出相加，进一步减少了逻辑综合的时间。结果，逻辑合成的时间减少到至少1/5，电路尺寸减少到至少1/4。由于f（x）依赖于设计，所以用可编程ASIC（FPGA）实现。基于这一特点，在现场使用的笔记本电脑上构建了一个原型开发系统，并成功地实现了采样频率为300 kHz的控制器。这一速度比使用DSP的软件控制器快约30倍。尽管控制器阶数为2，但即使阶数为20，采样率也不会低于200 kHz。如上所述，可以认为达到了在规模和时间上高效开发高阶硬件控制器的项目目标。一些设计方法与约束增益系数，以实现所需的规格，同时进一步减少电路尺寸，将在未来的研究。

Since software controllers are slow in high-order cases, such as in the H_* control, hardware is sometimes incorporated. Large circuit size, especially caused by multipliers, poses problems then. The project goal is to realize controllers with 100 times faster speed, by both reducing circuit and shortening the time of development.The actual mechanism is based on the fact that multiplication in controllers are usually with constant coefficients : multiplication k^* x is not considered to have two inputs, but is a function f(x) with x input only ; then, the circuit to derive f(x) from x is realized by logic synthesis.Linear operation of k1^* x1 + k2^* x2 + ... kn^* xn is implemented by combining synthesized constant coefficienters and an adder. Time of logic synthesis is further reduced by halving long input words and adding the two outputs. As a result, time of logic synthesis is reduced down to at least 1/5, circuit size to at least 1/4. In addition, a feature that their increments for order increment is linear is verified.Because f(x) depends on design, implementation is accomplished with programmable ASIC'S (FPGA's). Based on this feature, a prototype development system is constructed on a notebook PC to be used on site, and a controller with sample frequency of 300kHz is successfully implemented. This speed is about 30 times faster than software controllers with a DSP's. Though the controller order is 2, sample rate will be no slower than 200kHz even if the order is 20.As described, the project goal, to develop high-order hardware controllers efficiently in both size and time, is considered to be attained. Some design method with constrained gain coefficients, to realize the desired specification while further reducing circuit size, will be investigated in the future.