VERification-Driven Asynchronous Design (VERDAD)

验证驱动的异步设计 (VERDAD)

• 批准号: EP/G02930X/1
• 负责人: Stephen Furber
• 金额: $ 47.6万
• 依托单位: University of Manchester
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2009
• 资助国家: 英国
• 起止时间: 2009 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FG02930X%2F1
• 关键词: VERification; Driven; Asynchronous; Design; VERDAD

Abstracts are not currently available in GtR for all funded research. This is normally because the abstract was not required at the time of proposal submission, but may be because it included sensitive information such as personal details.

目前GtR中并没有所有资助研究的摘要。这通常是因为在提交提案时不需要摘要，但也可能是因为摘要中包含个人详细信息等敏感信息。

项目成果

SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC

• DOI: 10.1142/s021812661350028x
• 发表时间: 2013-04-01
• 期刊: JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
• 影响因子: 1.5
• 作者: Balasubramanian, P.;Edwards, D. A.;Toms, W. B.
• 通讯作者: Toms, W. B.

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

• DOI: 10.1155/2012/575389
• 发表时间: 2012
• 期刊: VLSI Design
• 作者: P. Balasubramanian;D. A. Edwards;W. Toms

Self-Timed Realization of Combinational Logic

组合逻辑的自定时实现

• 作者: P Balasubramanian (Author)