Ferroelectrics for Nanoelectronics (FERN)

自20世纪60年代以来，硅技术的发展主要集中在通过小型化每18-24个月将性能和功能翻一番。以几十纳米为尺度的关键尺寸现在很常见，数十亿个元件通过数英里长的线路连接在一起，可以被封装在一个指甲盖大小的晶圆上。今天的焦点已经从更多的可扩展性（以英特尔创始人戈登·摩尔的名字命名）转向通过在硅上引入混合技术来增加功能（称为“超越摩尔”）。本项目研究超薄铁电材料与硅纳米电子学的结合及其众多应用中的两个。电容是电荷随电压的变化率。这是电容器的决定性特性，在许多电子系统中是必需的，但相对较大。铁电体可以使电容器缩小三个数量级，因为它们的介电常数很高。更重要的是，它们的电容可以根据施加的电压而变化，因此可以制造非常小且可调谐的电容器，这可以在手持电子产品中找到应用，以减少功耗。如果它们能被集成到硅微芯片上，将会进一步节省空间。薄层有望产生更高的电容。然而，有证据表明，电容在50 nm以下开始减小，因为据说在与电极的界面附近形成了死层，但这可能是一种界面效应，可以通过工程来减轻。最近有实验证明，超薄铁电薄膜中存在有效的负电容。如果这种材料可以被整合到晶体管中，那么它将能够降低晶体管在开与关状态之间切换所需的电压（亚阈值斜率）。这将改变硅技术，使新一代更强大的单核处理器成为可能。现代计算机有双核或多核处理器。单核处理器会产生过多的热量，但对于许多应用来说仍然是可取的。电容在亚阈值斜率上设置了下限。其结果是，晶体管需要更大的外加电压才能打开和/或漏电流，因此永远不能完全关闭。当更多的晶体管被塞进相同的硅片面积时，这会导致功率损耗和发热增加，从而限制了元件密度。将具有负电容的铁电薄膜集成到晶体管的栅极中可以减小总电容，从而减小亚阈值摆幅。了解和生产高质量铁电超薄膜的需求对于这些应用中的每一个都是必不可少的。纽卡斯尔大学的原子层沉积（ALD）和帝国理工学院的脉冲激光沉积（PLD）将用于沉积铁电材料钛酸钡（BTO）和钛酸钡锶（BST）的薄膜。两者都允许原子级精度的沉积厚度。需要广泛的表征来评估这些铁电薄膜的质量。第一性原理计算机模拟将用于更好地理解电影和指导实验。沉积和热参数空间将被映射，以确定最佳的铁电性能为给定的限制，由硅制造。将采用最好的铁电薄膜来制造晶体管，以确认亚阈值斜率的降低。将展示集成到硅上的铁电电容器，量化每单位面积的电容增加，并检查保持高晶体管性能所需的制造限制。这也将有助于确定集成问题，其中还包括设备污染和铁电蚀刻的发展。

The evolution of silicon technology since the 1960's has focussed on doubling performance and functionality every 18-24 months through miniaturization. Critical dimensions measured in tens of nanometres are now common place and billions of components connected by miles of wiring can be packed onto a wafer no larger than a thumb nail. Today the focus is shifting away from more scaling (called more Moore after the founder of Intel, Gordon Moore) towards increasing functionality through the introduction of mixed technologies on silicon (called more than Moore). This project investigates the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two of its many applications.Capacitance is the rate of change of charge with voltage. It is the defining property of capacitors which are necessary in many electronic systems but are relatively large. Ferroelectrics can shrink capacitors by three orders of magnitude, because their electric permittivity is so high. More than that, their capacitance can be made to vary depending on the applied voltage so very small and tunable capacitors can be made, which can find applications in hand held electronics products in order to reduce power consumption. If they could be integrated onto a silicon microchip there would be further space savings. Thin layers are expected to produce even higher capacitance. However there is evidence that capacitance starts to reduce below 50 nm as dead layers are said to form near the interface with electrodes, but this may be an interface effect which can be lessened through engineering. Recently there has been experimental evidence that effective negative capacitance can be seen in ultra-thin ferroelectric films. If such material can be incorporated into a transistor then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub-threshold slope). This would transform silicon technology, allowing a new generation of more powerful single core processors. Modern computers have dual or multi-core processors. A single core processor would generate too much heat but is still desirable for many applications. Capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switch off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub-threshold swing. The need to understand and produce high quality ferroelectric ultra-thin films is imperative for each of these applications. Atomic Layer Deposition (ALD) at Newcastle and Pulsed Laser Deposition (PLD) at Imperial College will be used to deposit thin films of the ferroelectric materials barium titanate (BTO) and barium strontium titanate (BST). Both allow deposition thicknesses with atomic level precision. Extensive characterisation is needed to assess quality of these ferroelectric films. First principles computer simulation will be used to gain a better understanding of the films and to direct experiments. The deposition and thermal parameter space will be mapped to identify best ferroelectric properties for given constraints laid down by the silicon fabrication. Transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub-threshold slope. Ferroelectric capacitors integrated onto silicon will be demonstrated, quantifying the capacitance increase per unit area and examining the fabrication constraints needed to maintain high transistor performance. This will also help identify integration issues, which also include equipment contamination and the development of ferroelectric etches.