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Ferroelectrics for Nanoelectronics (FERN)

纳米电子学铁电体 (FERN)

基本信息

批准号：
EP/H023666/1
负责人：
Anthony O'Neill
金额：
$ 67.34万
依托单位：
Newcastle University
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2010
资助国家：
英国
起止时间：
2010 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FH023666%2F1
关键词：
Ferroelectrics Nanoelectronics FERN

项目摘要

The evolution of silicon technology since the 1960's has focussed on doubling performance and functionality every 18-24 months through miniaturization. Critical dimensions measured in tens of nanometres are now common place and billions of components connected by miles of wiring can be packed onto a wafer no larger than a thumb nail. Today the focus is shifting away from more scaling (called more Moore after the founder of Intel, Gordon Moore) towards increasing functionality through the introduction of mixed technologies on silicon (called more than Moore). This project investigates the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two of its many applications.Capacitance is the rate of change of charge with voltage. It is the defining property of capacitors which are necessary in many electronic systems but are relatively large. Ferroelectrics can shrink capacitors by three orders of magnitude, because their electric permittivity is so high. More than that, their capacitance can be made to vary depending on the applied voltage so very small and tunable capacitors can be made, which can find applications in hand held electronics products in order to reduce power consumption. If they could be integrated onto a silicon microchip there would be further space savings. Thin layers are expected to produce even higher capacitance. However there is evidence that capacitance starts to reduce below 50 nm as dead layers are said to form near the interface with electrodes, but this may be an interface effect which can be lessened through engineering. Recently there has been experimental evidence that effective negative capacitance can be seen in ultra-thin ferroelectric films. If such material can be incorporated into a transistor then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub-threshold slope). This would transform silicon technology, allowing a new generation of more powerful single core processors. Modern computers have dual or multi-core processors. A single core processor would generate too much heat but is still desirable for many applications. Capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switch off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub-threshold swing. The need to understand and produce high quality ferroelectric ultra-thin films is imperative for each of these applications. Atomic Layer Deposition (ALD) at Newcastle and Pulsed Laser Deposition (PLD) at Imperial College will be used to deposit thin films of the ferroelectric materials barium titanate (BTO) and barium strontium titanate (BST). Both allow deposition thicknesses with atomic level precision. Extensive characterisation is needed to assess quality of these ferroelectric films. First principles computer simulation will be used to gain a better understanding of the films and to direct experiments. The deposition and thermal parameter space will be mapped to identify best ferroelectric properties for given constraints laid down by the silicon fabrication. Transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub-threshold slope. Ferroelectric capacitors integrated onto silicon will be demonstrated, quantifying the capacitance increase per unit area and examining the fabrication constraints needed to maintain high transistor performance. This will also help identify integration issues, which also include equipment contamination and the development of ferroelectric etches.

自 20 世纪 60 年代以来，硅技术的发展重点是通过小型化，性能和功能每 18-24 个月翻一番。现在，以数十纳米为单位测量的关键尺寸已很常见，通过数英里的布线连接的数十亿个组件可以封装在不大于拇指指甲的晶圆上。如今，焦点已从更多的缩放（以英特尔创始人戈登·摩尔的名字称为“更多摩尔”）转向通过在硅上引入混合技术（称为“超过摩尔”）来增加功能。该项目研究将超薄铁电材料纳入硅纳米电子学及其众多应用中的两个。电容是电荷随电压的变化率。这是许多电子系统中必需的电容器的定义属性，但电容器相对较大。铁电体可以将电容器缩小三个数量级，因为它们的介电常数非常高。更重要的是，它们的电容可以根据所施加的电压而变化，因此可以制造非常小的可调谐电容器，这可以在手持电子产品中找到应用，以降低功耗。如果它们可以集成到硅微芯片上，将会进一步节省空间。薄层预计会产生更高的电容。然而，有证据表明，电容在 50 nm 以下开始减小，因为据说在与电极的界面附近形成了死层，但这可能是一种界面效应，可以通过工程来减轻。最近有实验证据表明，在超薄铁电薄膜中可以看到有效的负电容。如果这种材料可以合并到晶体管中，那么它将能够降低晶体管在导通和截止状态之间切换所需的电压（亚阈值斜率）。这将改变硅技术，允许新一代更强大的单核处理器。现代计算机具有双核或多核处理器。单核处理器会产生太多热量，但对于许多应用来说仍然是理想的选择。电容对亚阈值斜率设置了下限。结果是晶体管需要更大的施加电压才能导通和/或会泄漏电流，因此永远无法完全关闭。由于更多的晶体管被挤在同一块硅片上，这会导致功率损耗和发热增加，从而限制了元件密度。将具有负电容的铁电薄膜集成到晶体管的栅极中将减少总电容，从而减少亚阈值摆幅。对于这些应用中的每一个，都必须了解和生产高质量的铁电超薄膜。纽卡斯尔的原子层沉积（ALD）和帝国理工学院的脉冲激光沉积（PLD）将用于沉积铁电材料钛酸钡（BTO）和钛酸锶钡（BST）薄膜。两者都允许具有原子级精度的沉积厚度。需要进行广泛的表征来评估这些铁电薄膜的质量。第一原理计算机模拟将用于更好地理解电影并指导实验。将映射沉积和热参数空间，以确定针对硅制造所规定的给定约束的最佳铁电特性。晶体管将采用最好的铁电薄膜来制造，以确认亚阈值斜率的降低。将演示集成到硅上的铁电电容器，量化每单位面积的电容增加并检查维持高晶体管性能所需的制造限制。这也将有助于识别集成问题，其中还包括设备污染和铁电蚀刻的发展。