Platform: Strained Si / SiGe: Materials, Technology and Design

该平台资助将支持纽卡斯尔大学在应变Si/SiGe材料、技术和设计方面进行的研究。自1994年以来，EPSRC， EC和工业资助一直在该领域持续进行，发表了50多篇论文。全球半导体市场每年价值1000亿美元，为了在未来维持摩尔定律所需的原始处理能力，现在需要新的创新。应变Si/SiGe CMOS技术一直在寻求应对这一挑战。在硅片上沉积一层厚厚的硅锗，使其松弛，形成虚拟衬底。随后在虚拟衬底上生长的硅薄层成为拉伸应变，而SiGe外延层可能是压缩的（如果Ge含量高于虚拟衬底）或拉伸的（如果Ge含量低于虚拟衬底）。应变Si/SiGe器件中更高的载流子迁移率可以通过更高的速度（无需重新加工）、更大的扇出或更低的功耗来实现。我们的长期目标是在新材料、设备和系统设计的协同作用领域建立一个国际卓越中心。具体主题包括：材料生长、临界厚度、扩散、缺陷、器件缩放、应变预算设计、MOSFET栅极堆、器件和工艺建模、电气特性、应变特性、掺杂特性、鲁棒设计和技术驱动电路设计中的可变性。

This Platform Grant will sustain research being carried out at Newcastle University in strained Si/SiGe materials, technology and design. EPSRC, EC and industrial funding has been continuous in this field since 1994, resulting in the publication of more than 50 papers. The world market for semiconductors is counted in $100 Billion's per year and new innovations are now necessary to deliver the raw processing power needed to maintain Moore's Law in the future. Strained Si/SiGe CMOS technology has been pursued to meet this challenge. A thick layer of SiGe deposited on a Si wafer, so that it is relaxed, forms a virtual substrate. A thin layer of Si grown subsequently on the virtual substrate becomes tensile strained, while SiGe epitaxial layers may be either compressive (if the Ge content is above that of the virtual substrate) or tensile (if the Ge content is below that of the virtual substrate). The higher carrier mobility seen in strained Si/SiGe devices can be exploited through higher speed (without re-tooling), larger fan-out or lower power. Our long-term goal is to build an international centre of excellence in the area of synergy between new materials, devices and system design. Specific topics include: material growth, critical thickness, diffusion, defects, device scaling, strain budget design, MOSFET gate stacks, device and process modelling, electrical characterisation, strain characterisation, doping characterisation, robust design and variability in technology-driven design of circuits.