Atomic Layer Interface Engineering for Nanoelectronics (ALIEN): Contacts

这项研究考虑了使用绝缘体来提高导电性的有趣前景。在过去的50年里，电子学的革命在很大程度上要归功于半导体，包括用于微芯片的硅，用于激光或led等光学元件的III-V半导体以及用于大面积显示器的有机半导体。从金属到这些半导体的电接触是基本的。肖特基和莫特在20世纪30年代提出并至今仍在教授的传统理论认为，电子在金属和半导体之间的连接处遇到的势能势垒只是从每种材料中获取电子所需的能量差（功函数差）。因此，通过适当选择半导体和金属，从其中任何一方移出电子的能量将是相同的，并且它们之间应该没有电流障碍。但经验表明，情况通常并非如此，尤其是对具有商业利益的半导体而言。事实上，势能势垒（肖特基势垒）对于任何给定半导体的所有金属接触都趋于相同。这种效应被称为费米能级钉住，它的产生是因为金属中的电子溢出到连接处的半导体中。屏障产生电阻，根据电流的方向可能不同（肖特基二极管）。通过增大接触表面积和/或增加半导体中的掺杂，使得势能势垒变得足够薄，电子可以很容易地隧穿，从而降低电阻。但这并不总是可能的或充分的。改善电接触的一种新方法是在金属和半导体之间加一层薄绝缘体。其效果是防止电子从金属中溢出到半导体中，从而防止费米能级固定。正如肖特基-莫特理论所指出的那样，正确选择金属和半导体可以降低势能垒的高度。一个复杂的问题是，绝缘体本身可能会阻挡电流，因此需要很薄（~ nm尺度）。这项研究将在半导体和金属之间沉积纳米级的绝缘层，以改善接触面上的传导。一系列的实验技术将用于测量由薄绝缘体膜带来的电性能变化，并且薄膜厚度将针对一系列重要的半导体进行优化。对金属、绝缘体和半导体的原子结构进行建模，将有助于揭示在改善电流流动中起作用的相互竞争的因素。该研究还将解决将这种类型的接触集成到制造设备，3D结构中，并测试其对有机半导体的适用性。

This research considers the intriguing prospect of using insulators to improve electrical conductivity. The revolution in electronics over the last 50 years is due in large part to semiconductors, including silicon for microchips, III-V semiconductors for optical components such as lasers or LEDs and organic semiconductors for large area displays. Electrical contact from a metal to these semiconductors is fundamental. Conventional theory, developed by Schottky and Mott in the 1930's and still taught today, says that the potential energy barrier that electrons encounter at the junction between a metal and a semiconductor is simply the difference in energy needed to take electrons from each material (the workfunction difference). Thus by a suitable choice of semiconductor and metal, the energy to remove electrons from either will be the same and there should be no barrier to current between them. But experience shows this is generally not the case, particularly for semiconductors of commercial interest. In fact, the potential energy barrier (the Schottky barrier) tends to be about the same for all metal contacts to any given semiconductor. The effect is called Fermi level pinning and arises because electrons from the metal spill into the semiconductor at the junction. The barrier gives rise to an electrical resistance, which may be different depending on the direction of current (a Schottky diode). The resistance can belowered by making the contact surface area large and/or by increasing doping in the semiconductor so that the potential energy barrier becomes thin enough that electrons can easily tunnel through. But this is not always possible or sufficient. A novel approach to improving the electrical contact is to add a thin insulator in between the metal and the semiconductor. The effect is to prevent electrons spilling from the metal into the semiconductor and so prevent Fermi level pinning. The correct choice of metal and semiconductor will allow a reduction in potential energy barrier height, as Schottky-Mott theory suggests. A complication is that the insulator itself may block current and so needs to be thin (~ nm scale). This research will deposit nm scale insulating layers between semiconductors and metals to improve conduction across the contact. A range of experimental techniques will be used to measure the change in electrical properties brought about by the thin insulator films and the film thickness will be optimised for a range of important semiconductors. Modelling of the atomic structure of the metal, insulator and semiconductor will help to unravel to competing factors that are at play in improving current flow. The research will also address integrating this type of contact into a manufactured device, 3D structures and to test its applicability to organic semiconductors.