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PAnDA: Programmable Analogue and Digital Array

PAnDA：可编程模拟和数字阵列

基本信息

批准号：
EP/I005838/1
负责人：
Andy Tyrrell
金额：
$ 155.54万
依托单位：
University of York
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2010
资助国家：
英国
起止时间：
2010 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FI005838%2F1
关键词：
PAnDA Programmable Analogue Digital Array

项目摘要

Moore's law states that, since their invention in 1947, every two years the number of transistors on an integrated circuit doubles. This is due to the shrinking of devices through advances in technology. However, as these devices are approaching the atomistic level, intrinsic variations are becoming more abundant, leading to a lower production yield and higher failure rates. In order to accommodate the increased variability of individual device characteristics there is a need for novel device architectures and circuit design methodologies. For example, Intel were forced to make the biggest change in transistor technology since the 1960s in order to reach the 45nm CMOS technology node. These predictions and issues were originally focussed on large-scale integration, mainly connected with microprocessor design. However, in the last 10 years the rise of Field Programmable devices (e.g. Field Programmable Gate Arrays - FPGA) both in terms of technology advances and application domains has meant that these issues are now relevant to these devices as well. Hence, the proposal focuses upon one of the current greatest challenges in electronic design: taking physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels, in order to achieve functional circuit designs. Both process and substrate variations impose major challenges on the reliable fabrication of such small devices. These variations fall into two categories; deterministic variability, which can be accurately modelled and accounted for using specific design techniques, and stochastic variability, which can only be modelled statistically and is harder to overcome. The proposal will develop a reconfigurable design platform that can be manipulated at the device and digital abstraction levels in order to further understand and tackle the effects of stochastic variability in hardware upon next generation designs.The research proposal comprises four threads that build upon each other:- Design of a simulation model for a variability tolerant architecture, - Hardware realisation of this model,- Development of a comprehensive software framework, which will be able to interface the simulation model as well as the chip,- Development of bio-inspired approaches to tackle variability tolerant design. At its conclusion the project will have developed an understanding of how stochastic variability will affect circuit design in the future and will propose novel design methodologies to overcome stochastic variability. A novel, variability tolerant architecture will have been developed and realised as a simulation model and as a prototype in hardware. Both are vital steps towards next generation FPGA architectures.

摩尔定律指出，自1947年发明晶体管以来，集成电路上的晶体管数量每两年增加一倍。这是由于通过技术进步缩小了设备。然而，随着这些器件接近原子水平，固有的变化变得越来越丰富，导致更低的生产良率和更高的故障率。为了适应个体器件特性的增加的可变性，需要新颖的器件架构和电路设计方法。例如，英特尔被迫在晶体管技术上做出自20世纪60年代以来最大的改变，以达到45纳米CMOS技术节点。这些预测和问题最初集中在大规模集成上，主要与微处理器设计有关。然而，在过去10年中，现场可编程器件（例如现场可编程门阵列- FPGA）在技术进步和应用领域方面的兴起意味着这些问题现在也与这些器件相关。因此，该提案侧重于当前电子设计中最大的挑战之一：当器件尺寸缩小接近原子水平时，考虑固有可变性的物理效应，以实现功能电路设计。工艺和衬底的变化都对此类小型器件的可靠制造带来了重大挑战。这些变化分为两类：确定性变化，可以使用特定的设计技术准确建模和解释，以及随机变化，只能通过统计建模，更难克服。该研究计划将开发一个可重新配置的设计平台，该平台可以在设备和数字抽象层面进行操作，以进一步了解和解决硬件随机变化对下一代设计的影响。该研究计划包括四个相互建立的线程：- 设计用于可变性容限架构的仿真模型，-该模型的硬件实现，-开发综合软件框架，其将能够与仿真模型以及芯片接口，- 开发生物启发的方法，以解决可变性容限设计。在其结束时，该项目将制定一个理解如何随机可变性将影响电路设计在未来，并将提出新的设计方法，以克服随机可变性。一种新的，可变性容忍架构将被开发和实现作为一个仿真模型，并在硬件中作为原型。两者都是迈向下一代FPGA架构的重要步骤。