Quantitative Hall Voltage mapping at conducting Ferroelectric domain walls: A novel approach to extracting conduction mechanisms on the nanoscale

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The remarkable ability of ferroelectric domain walls, boundaries that separate regions of uniform electrical polarisation, to conduct electrical current has opened up dramatic possibilities for their use in nanoelectronics. Reconfigurable ferroelectric domain wall-based nanoelectronics, where unique electronic properties of conductive and simultaneously mobile domain walls can be exploited towards functional devices, represents a truly novel and disruptive approach to existing norms of electronics. In 2017, the Engineering and Physical Sciences Research Council (EPSRC) has funded a four year programme for teams across four institutions (Belfast, Warwick, St Andrews and Cambridge), to investigate novel functional properties in ferroelectric and multiferroic domain walls. A major thrust of this effort is the exploration of the fundamental physics of transport seen in domain walls. As part of this work, carrier types, densities and mobilities are being mapped for domain walls in a number of different materials systems using a new form of scanning probe microscopy, in which the Hall voltage is measured, with nanoscale spatial resolution, using Kelvin Probe Force Microscopy (KPFM). KPFM works by balancing different levels of surface potential on the sample with equal tip potentials, supplied by the atomic force microscope (AFM) itself. In all standard AFMs, the range of internal bias that can be supplied to the tip is +/- 10V, limiting the surface potential that can be mapped to the same range. For our nanoscale domain wall measurements, current is driven along the walls, in the presence of a perpendicular magnetic field, and the resultant Hall Potential is measured along the lines of intersection between the domain walls and the top surfaces of the samples. For systems in which the domain wall conductivity is large, sufficient current to allow a measurable Hall signal, can de driven using modest source-drain potential differences. Frustratingly, for domain walls with lower conductivities, the source-drain potential difference needed to drive sufficient current for measurable Hall signals needs to be significantly larger: up to the order of 50-100V and beyond the range at which internal AFM electronics can supply a balancing bias and hence detect the true potential on the surface . Thus, while we have been able to make categorical measurements of the Hall Effect for domain walls with good conductivity, we have been unable to perform equivalent measurements in systems such as Cu-Cl boracite, LiNbO3, lead germanate and undoped manganites, where equivalent measurements and physical insight into conductivity mechanisms are lacking. This limitation of the Hall voltage microscopy approach can be overcome if a higher voltage (> +/- 10V) can be applied and detected seamlessly by the hardware/electronics configured for the AFM. The manufacturers of the AFM, Asylum Research, have recently started offering a HV module capable of applying voltages between -150V and +150V which could be adapted by our relevant expertise in Hall voltage microscopy to perform fully quantitative Hall potential mapping in the higher voltage regime. This proposal aims to upgrade our AFM with a HV module and subsequently adapt it to perform high-voltage KPFM based Hall voltage mapping at conducting ferroelectric domain walls to allow fundamental insight into the physics of transport at conducting walls across a significantly wider range of ferroelectrics than currently possible. The developed measurement techniques will remove a significant hurdle in directly extracting relevant carrier information and mechanisms of electrical conduction at conducting domain walls in the majority of bulk and thin-film ferroelectrics of interest for domain wall based nanoelectronics. The techniques developed here could also facilitate direct and relatively easy-to-use means for nanoscale spatially resolved mapping of carrier profiles in the existing electronics industry.