Novel Device, Circuit and System Design Concepts utilising Innovative Nanoscale CMOS Devices for Low Voltage Analog/RF Applications

35年来，集成电路（IC）行业一直在快速、一致地扩展设计规则，并改进器件和电路的设计。结果，半导体工业已经享受到芯片速度和功能密度随时间的指数增长，以及功率耗散和每个功能的成本的指数下降，如摩尔定律所预测的。然而，由于某些关键器件、材料和工艺限制，例如本征参数波动、增加的短沟道效应（SCE）、增加的寄生串联电阻和薄无缺陷硅膜的制造，该行业在继续将全耗尽MOSFET按比例缩小到纳米级尺寸方面面临越来越多的困难。为了克服这些限制，已经提出了多栅极器件（MuGFET），其中由于增强短沟道抗扰性的有效栅极控制而放宽了使用超薄硅膜的要求。FinFET是特别流行的MuGFET，其中电流在源极和漏极之间水平地（平行于衬底的平面）流动，沿着相对的垂直沟道表面。新颖的纳米级3D MOS结构需要非经典的独特效应，例如非垂直侧壁、非自对准栅极、拐角效应、量子效应、源极/漏极（S/D）扩展区工程、本征和非本征寄生电阻和电容，精确建模和模拟，以理解和优化器件结构。理想化器件的传统假设忽略了这些高度占主导地位的非经典独特效应，这些效应在纳米级范围内严格控制着MuGFET的行为。必须准确模拟这些效应，以评估MuGFET在数字、模拟和高频应用中的优势和挑战。拟议的研究将通过全面的物理器件模拟，包括内在和外在参数，详细的宽带实验表征和参数提取技术，以及为ITRS路线图结束时的半导体行业提供解决方案，来了解这些器件的性能。最终成果将是纳米级MuGFET的3D参数化模拟，包括所有相关的固有和非固有寄生效应，改进的载流子传输物理模型以及对静态和动态应用的新沟道材料和栅漏的评估。这项工作将在北方爱尔兰半导体研究中心、女王大学贝尔法斯特进行，并将其正在进行的硅化物、金属栅和高k值半导体的实验研究项目联系起来。该项目将与法国微电子、电磁学和光子学研究所、英国北泰恩赛德ATMEL、比利时鲁汶天主教大学和美国国家半导体公司合作开展。

The integrated circuit (IC) industry has been rapidly and consistently scaling the design rules and improving the design of devices and circuits for over 35 years. As a result, the semiconductor industry has enjoyed exponential increase in chip speed and functional density with time, combined with an exponential decrease in power dissipation and cost per function, as projected by Moore's Law. However, the industry is facing increasing difficulties in continuing to scale down fully depleted MOSFETs to nanoscale dimensions owing to certain key device, material and process limits such as intrinsic parameter fluctuations, increased short channel effects (SCEs), increased parasitic series resistance and fabrication of thin defect free silicon film. To overcome these limitations, multiple gate devices (MuGFETs) have been proposed, where the requirement of using ultra thin silicon film is relaxed due to efficient gate control that enhances short channel immunity. The FinFET is a particularly popular MuGFET in which current flows horizontally (parallel to the plane of the substrate) between the source and drain, along opposite vertical channel surfaces. A lithographically defined gate straddles the fin, forming self-aligned, electrically connected gate electrodes along the sidewalls of the fin.Novel nanoscale 3D MOS structures require non-classical distinctive effects such as non vertical sidewalls, non self-aligned gates, corner effects, quantum effects, source/drain (S/D) extension region engineering, intrinsic and extrinsic parasitic resistances and capacitances, to be accurately modelled and simulated to understand and optimise the device structure. Traditional assumptions for idealised devices ignore these highly dominant non-classical distinctive effects that critically govern the behaviour of MuGFETs in the nanoscale regime. These effects must be accurately simulated in order to assess the advantages and challenges of MuGFETs for digital, analog and high frequency applications. The proposed research will provide an understanding of the performance of these devices by means of comprehensive physical device simulations including intrinsic and extrinsic parameters, detailed broadband experimental characterisation and parameter extraction techniques as well as provide solutions to the semiconductor industry for devices at the end of ITRS roadmap and beyond. The final outcome will be 3D parameterised simulation of nanoscale MuGFETs with inclusion of all relevant intrinsic and extrinsic parasitics, improved physical models for carrier transport and the assessment of new channel materials and gate dielectrics for static and dynamic applications. The work will be carried out at Northern Ireland Semiconductor Research Centre, Queen's University Belfast and linked its ongoing experimental research projects on silicides, metal gate and high-k dielectrics. The project will carried out in collaboration with Institute of Microelectronics, Electromagnetism and Photonics, France, ATMEL North Tyneside, UK, Universit catholique de Louvain, Belgium and National Semiconductor USA.