Novel Device, Circuit and System Design Concepts utilising Innovative Nanoscale CMOS Devices for Low Voltage Analog/RF Applications

35年来，集成电路(IC)行业一直在快速一致地调整设计规则，改进器件和电路的设计。因此，按照摩尔定律的预测，半导体行业的芯片速度和功能密度随时间呈指数级增长，同时功耗和每功能成本呈指数级下降。然而，由于某些关键器件、材料和工艺的限制，如本征参数波动、增加的短沟道效应(SCE)、增加的寄生串联电阻和薄的无缺陷硅膜的制备，该行业在继续将完全耗尽的MOSFET缩小到纳米尺寸方面面临着越来越多的困难。为了克服这些限制，人们提出了多栅极器件(MuGFET)，其中由于有效的栅极控制增强了短沟道抗扰性，因此放宽了对使用超薄硅膜的要求。FinFET是一种特别流行的MuGFET，其中电流沿相反的垂直沟道表面在源极和漏极之间水平(平行于衬底平面)流动。新型纳米级3D MOS结构需要对非经典的独特效应，如非垂直侧壁、非自对准栅极、角效应、量子效应、源/漏(S/D)扩展区工程、本征和外在寄生电阻和电容等进行准确的建模和模拟，以了解和优化器件结构。理想化器件的传统假设忽略了这些高度主导的非经典独特效应，这些效应对纳米尺度下MuGFET的行为起着至关重要的支配作用。必须准确地模拟这些效应，以便评估MuGFET在数字、模拟和高频应用中的优势和挑战。拟议的研究将通过全面的物理器件模拟(包括内部和外部参数、详细的宽带实验表征和参数提取技术)来了解这些器件的性能，并为半导体行业在ITRS路线图结束时及以后的器件提供解决方案。最终结果将是纳米级MuGFET的3D参数模拟，包括所有相关的内在和外在寄生因素，改进的载流子传输物理模型，以及静态和动态应用的新沟道材料和栅电介质的评估。这项工作将在贝尔法斯特女王大学北爱尔兰半导体研究中心进行，并将其正在进行的硅化物、金属栅和高k电介质的实验研究项目联系起来。该项目将与法国微电子、电磁和光子学研究所、英国爱特梅尔北泰恩赛德大学、比利时卢万大学和美国国家半导体公司合作进行。

The integrated circuit (IC) industry has been rapidly and consistently scaling the design rules and improving the design of devices and circuits for over 35 years. As a result, the semiconductor industry has enjoyed exponential increase in chip speed and functional density with time, combined with an exponential decrease in power dissipation and cost per function, as projected by Moore's Law. However, the industry is facing increasing difficulties in continuing to scale down fully depleted MOSFETs to nanoscale dimensions owing to certain key device, material and process limits such as intrinsic parameter fluctuations, increased short channel effects (SCEs), increased parasitic series resistance and fabrication of thin defect free silicon film. To overcome these limitations, multiple gate devices (MuGFETs) have been proposed, where the requirement of using ultra thin silicon film is relaxed due to efficient gate control that enhances short channel immunity. The FinFET is a particularly popular MuGFET in which current flows horizontally (parallel to the plane of the substrate) between the source and drain, along opposite vertical channel surfaces. A lithographically defined gate straddles the fin, forming self-aligned, electrically connected gate electrodes along the sidewalls of the fin.Novel nanoscale 3D MOS structures require non-classical distinctive effects such as non vertical sidewalls, non self-aligned gates, corner effects, quantum effects, source/drain (S/D) extension region engineering, intrinsic and extrinsic parasitic resistances and capacitances, to be accurately modelled and simulated to understand and optimise the device structure. Traditional assumptions for idealised devices ignore these highly dominant non-classical distinctive effects that critically govern the behaviour of MuGFETs in the nanoscale regime. These effects must be accurately simulated in order to assess the advantages and challenges of MuGFETs for digital, analog and high frequency applications. The proposed research will provide an understanding of the performance of these devices by means of comprehensive physical device simulations including intrinsic and extrinsic parameters, detailed broadband experimental characterisation and parameter extraction techniques as well as provide solutions to the semiconductor industry for devices at the end of ITRS roadmap and beyond. The final outcome will be 3D parameterised simulation of nanoscale MuGFETs with inclusion of all relevant intrinsic and extrinsic parasitics, improved physical models for carrier transport and the assessment of new channel materials and gate dielectrics for static and dynamic applications. The work will be carried out at Northern Ireland Semiconductor Research Centre, Queen's University Belfast and linked its ongoing experimental research projects on silicides, metal gate and high-k dielectrics. The project will carried out in collaboration with Institute of Microelectronics, Electromagnetism and Photonics, France, ATMEL North Tyneside, UK, Universit catholique de Louvain, Belgium and National Semiconductor USA.