CAREER: Opportunistic Through-Silicon-Via Utilization: Device, Circuit and Design Automation Perspectives

职业:机会性硅通孔利用:器件、电路和设计自动化视角

基本信息

  • 批准号:
    1559026
  • 负责人:
  • 金额:
    $ 37.56万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2015
  • 资助国家:
    美国
  • 起止时间:
    2015-09-01 至 2019-02-28
  • 项目状态:
    已结题

项目摘要

The three-dimensional integrated circuit (3D IC) stacks multiple dies in the vertical dimension using Through-Silicon-Vias (TSVs), which results in significantly reduced footprint, power and latency. While many challenges still exist related to 3D ICs, this project targets the one challenge that will become increasingly important in the next 5 to 10 years and may potentially end the production of 3D ICs: TSVs are quite large in size, yet their diameters do not scale with the devices due to the limitations of wafer handling and aspect ratios. On the other hand, a large number of TSVs are needed to deliver signal and power, to dissipate heat, and to provide redundancy. Moreover, foundries impose a minimum TSV density rule to maintain the planarity of the wafer during chemical and mechanical polishing (CMP). This project tackles the challenge by reconfiguring idle TSVs as devices for various circuits and systems. An opportunistic computer-aided design (CAD) framework will also be put forward for optimum utilization of the TSV devices. The proposed research will pioneer a new and transformative direction for the advancement of 3D ICs at all the design levels - devices, circuits and CAD - with no change required in current semiconductor processes. The PI will also leverage the collaboration with Industrial Technology Research Institute to set up an extensive international internship program for U.S. undergraduates and graduates, which will benefit the general 3D IC research community. In addition, the PI will develop various activities for undergraduates and underrepresented minorities within the research framework, full-filled 3D Tetris contests for Rolla local high school students, and a web 2.0-based 3D forum for collaborative research in the 3D IC community.
三维集成电路(3D IC)使用硅通孔(TSV)在垂直维度上堆叠多个管芯,这导致显著减小的占用面积、功率和延迟。虽然3D IC仍存在许多挑战,但该项目针对的是未来5至10年将变得越来越重要并可能终止3D IC生产的一个挑战:TSV尺寸相当大,但由于晶圆处理和纵横比的限制,它们的直径与器件不成比例。另一方面,需要大量TSV来传递信号和功率、散热以及提供冗余。此外,代工厂施加最小TSV密度规则以在化学和机械抛光(CMP)期间保持晶片的平面性。该项目通过将空闲TSV重新配置为各种电路和系统的器件来应对挑战。一个机会的计算机辅助设计(CAD)框架也将提出TSV器件的最佳利用。拟议的研究将为3D IC在所有设计层面(器件、电路和CAD)的进步开辟一个新的变革方向,而不需要改变当前的半导体工艺。PI还将利用与工业技术研究院的合作,为美国本科生和研究生建立一个广泛的国际实习计划,这将有利于一般的3D IC研究社区。此外,PI将在研究框架内为本科生和代表性不足的少数族裔开发各种活动,为罗拉当地高中生举办内容丰富的3D俄罗斯方块比赛,以及基于Web 2.0的3D论坛,用于3D IC社区的合作研究。

项目成果

期刊论文数量(0)
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Yiyu Shi其他文献

DLBC: A Deep Learning-Based Consensus in Blockchains for Deep Learning Services
DLBC:深度学习服务区块链中基于深度学习的共识
  • DOI:
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Boyang Li;Changhao Chenli;Xiaowei Xu;Yiyu Shi;Taeho Jung
  • 通讯作者:
    Taeho Jung
Optimizing sequential diagnostic strategy for large-scale engineering systems using a quantum-inspired genetic algorithm: A comparative study [J]. , 2019(12). (SCI)
使用量子启发遗传算法优化大型工程系统的顺序诊断策略:比较研究[J]。
  • DOI:
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    8.7
  • 作者:
    Jinsong Yu;Yiyu Shi;Diyin Tang;Hao Liu;Limei Tian
  • 通讯作者:
    Limei Tian
HS3-DPG: Hierarchical Simulation for 3-D P/G Network
HS3-DPG:3-D P/G 网络的分层仿真
Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding
利用时分复用和随机编码对抗商业和 ASIC 应用中的数据泄露木马
Optimal selected phasor measurement units for identifying multiple line outages in smart grid
用于识别智能电网中多条线路停电的最佳选择相量测量单元

Yiyu Shi的其他文献

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{{ truncateString('Yiyu Shi', 18)}}的其他基金

Collaborative Research: DESC: Type II: REFRESH: Revisiting Expanding FPGA Real-estate for Environmentally Sustainability Heterogeneous-Systems
合作研究:DESC:类型 II:REFRESH:重新审视扩展 FPGA 空间以实现环境可持续性异构系统
  • 批准号:
    2324865
  • 财政年份:
    2023
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
FuSe-TG: Cross-layer Co-Design for Self-Evolving Implantable Devices
FuSe-TG:自我进化植入设备的跨层协同设计
  • 批准号:
    2235364
  • 财政年份:
    2023
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
IRES Track I: International Research Experience for Students on Artificial Intelligence for Congenital Heart Diseases
IRES Track I:先天性心脏病人工智能学生国际研究经验
  • 批准号:
    2106416
  • 财政年份:
    2021
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
Collaborative Research: CNS Core: Small: Towards Unsupervised Learning on Resource Constrained Edge Devices with Novel Statistical Contrastive Learning Scheme
合作研究:CNS 核心:小型:利用新颖的统计对比学习方案在资源受限的边缘设备上实现无监督学习
  • 批准号:
    2122220
  • 财政年份:
    2021
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
RAPID: Collaborative Research: Independent Component Analysis Inspired Statistical Neural Networks for 3D CT Scan Based Edge Screening of COVID-19
RAPID:协作研究:独立成分分析启发的统计神经网络,用于基于 3D CT 扫描的 COVID-19 边缘筛查
  • 批准号:
    2027539
  • 财政年份:
    2020
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
Collaborative Research: CNS Core: Small: Intermittent and Incremental Inference with Statistical Neural Network for Energy-Harvesting Powered Devices
合作研究:CNS 核心:小型:利用统计神经网络对能量收集供电设备进行间歇和增量推理
  • 批准号:
    2007302
  • 财政年份:
    2020
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
SPX: Collaborative Research: Scalable Neural Network Paradigms to Address Variability in Emerging Device based Platforms for Large Scale Neuromorphic Computing
SPX:协作研究:可扩展神经网络范式,以解决基于新兴设备的大规模神经形态计算平台的可变性
  • 批准号:
    1919167
  • 财政年份:
    2019
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
Phase 1 IUCRC University of Notre Dame: Center for Alternative Sustainable and Intelligent Computing (ASIC)
第一阶段 IUCRC 圣母大学:替代可持续和智能计算中心 (ASIC)
  • 批准号:
    1822099
  • 财政年份:
    2018
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Continuing Grant
University of Notre Dame Planning Grant: I/UCRC for Alternative Sustainable and Intelligent Computing (ASIC)
圣母大学规划补助金:I/UCRC 替代可持续和智能计算 (ASIC)
  • 批准号:
    1650473
  • 财政年份:
    2017
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant
IRES: International Research Experience for Students on Design Automation of Three-Dimensional Integrated Circuits
IRES:三维集成电路设计自动化学生国际研究经验
  • 批准号:
    1456867
  • 财政年份:
    2015
  • 资助金额:
    $ 37.56万
  • 项目类别:
    Standard Grant

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