CAREER: Opportunistic Through-Silicon-Via Utilization: Device, Circuit and Design Automation Perspectives

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The three-dimensional integrated circuit (3D IC) stacks multiple dies in the vertical dimension using Through-Silicon-Vias (TSVs), which results in significantly reduced footprint, power and latency. While many challenges still exist related to 3D ICs, this project targets the one challenge that will become increasingly important in the next 5 to 10 years and may potentially end the production of 3D ICs: TSVs are quite large in size, yet their diameters do not scale with the devices due to the limitations of wafer handling and aspect ratios. On the other hand, a large number of TSVs are needed to deliver signal and power, to dissipate heat, and to provide redundancy. Moreover, foundries impose a minimum TSV density rule to maintain the planarity of the wafer during chemical and mechanical polishing (CMP). This project tackles the challenge by reconfiguring idle TSVs as devices for various circuits and systems. An opportunistic computer-aided design (CAD) framework will also be put forward for optimum utilization of the TSV devices. The proposed research will pioneer a new and transformative direction for the advancement of 3D ICs at all the design levels - devices, circuits and CAD - with no change required in current semiconductor processes. The PI will also leverage the collaboration with Industrial Technology Research Institute to set up an extensive international internship program for U.S. undergraduates and graduates, which will benefit the general 3D IC research community. In addition, the PI will develop various activities for undergraduates and underrepresented minorities within the research framework, full-filled 3D Tetris contests for Rolla local high school students, and a web 2.0-based 3D forum for collaborative research in the 3D IC community.