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Semi-insulating Silicon substrates for high frequency integrated circuits

高频集成电路用半绝缘硅衬底

基本信息

批准号：
EP/F033311/1
负责人：
Cornelis Hendrik De Groot
金额：
$ 39.33万
依托单位：
University of Southampton
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2008
资助国家：
英国
起止时间：
2008 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FF033311%2F1
关键词：
Semi insulating Silicon substrates frequency

项目摘要

Semi-insulating silicon substrates would be very attractive as handle wafers in Silicon On Insulator (SOI) technologies because they would provide very low-absorption substrates for RF and monolithic microwave integrated circuits. Two of the investigators have previously theoretically analysed the effect of different deep level impurities on silicon resistivity and shown that a resistivity of nearly 100kOhm.cm should be achievable by dopant compensation. This theoretical work has been supported by our recently published experimental feasibility study that has delivered a very promising resistivity value of 12kohm.cm using Mn as the deep level impurity. This proposal aims to study the science and engineering of high resistivity silicon substrates for high frequency integrated circuits. The team encompasses expertise on the materials science of deep level impurities (University of Oxford), on the physics and technology of high frequency silicon devices (University of Southampton), on silicon wafer growth (MEMC) and on the design and fabrication of high frequency integrated circuits (Zarlink). The project aims to better understand the diffusion and doping vs resistivity relations of appropriate deep level impurities (including Mn), and hence to maximise the resistivity of the silicon handle wafer. Contamination issues arising from the deep level impurities will be addressed by investigating diffusion barriers and also by developing a back-end processing approach that takes advantage of the high diffusivity of some deep level impurities. The recent incorporation of Cu metallization into back-end silicon production processes suggests that other deep level impurities would not be seen by industry as a major contamination issue in back-end processing. Finally, SOI wafers will be fabricated on semi-insulating silicon substrates and detailed high frequency characterisation carried out.

半绝缘硅衬底作为绝缘体上硅（SOI）技术中的处理晶片将是非常有吸引力的，因为它们将为RF和单片微波集成电路提供非常低的吸收衬底。两名研究人员先前已经从理论上分析了不同深能级杂质对硅电阻率的影响，并表明通过掺杂剂补偿应该可以实现接近100kOhm.cm的电阻率。我们最近发表的实验可行性研究支持了这一理论工作，该研究使用Mn作为深能级杂质提供了非常有希望的电阻率值。12kohm.cm本提案旨在研究高频集成电路用高电阻率硅衬底的科学和工程。该团队包括深层次杂质材料科学（牛津大学），高频硅器件物理和技术（南安普顿大学），硅晶片生长（MEMC）和高频集成电路设计和制造（Zarlink）的专业知识。该项目旨在更好地了解适当的深能级杂质（包括Mn）的扩散和掺杂与电阻率的关系，从而最大限度地提高硅处理晶片的电阻率。由深层次的杂质所产生的污染问题将通过调查扩散障碍，也通过开发一个后端处理方法，利用一些深层次的杂质的高扩散性来解决。最近将Cu金属化结合到后端硅生产工艺中表明，其他深能级杂质不会被工业视为后端处理中的主要污染问题。最后，将在半绝缘硅衬底上制造SOI晶片，并进行详细的高频表征。