Design and VLSI implementations of DSP algorithms for communication systems

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The proposed research will leverage the invistigation of innovative solutions in the design and VLSI implementations of digital signal processing (DSP) algorithms for communication systems. Solutions that would lead to high performance, low complexity and low-power consumptions will be adopted. Objectives of the project are: (1) To further develop blind equalization techniques that have shorter time-to-convergence (TTC) quality to suit high-speed communication systems and for other  modulation schemes implemented in wireless communication standards (i.e., DPSK, DQPSK, GMSK, etc.). (2) To further develop computationally-efficient blind adaptive equalization techniques that reduce both the amount of computations and hence increase the system's throughput, and/or decrease hardware complexity. (3)To develop programmable/reconfigurable blind adaptive equalizer so that their filter lengths, adaptation parameters, and error measure are variables according to the modulation utilized in the receiver for multi-standard future communication equipments (also as in software-defined radios). (4) To develop low-lardware-complexity and/or computationally-efficient adaptive algorithms for echo cancellation applications in communication systems. (5)To achieve low-power in blind adaptive equalizers and adaptive echo cancellers (AECs) to respond to the increased demand of fast-growing mobile communication services. (6)To develop VLSI implementations of blind adaptive equalizers and echo cancellers that incorporate both high-speed, low-power, and low-complexity requirements. (7) To achieve performance enhancement and robustness of 802.11a/RA for high vehicular velocity, so that higher data rates may be achieved in a 5.9GHz Dedicated Short Range Communication (DSRC) system.   (8)To confirm feasibility, consider the complexity of the receiver design, and maintain consistency with the 802.11a/RA standard.