Design and VLSI implementations of DSP algorithms for communication systems

通信系统 DSP 算法的设计和 VLSI 实现

• 批准号: 288185-2006
• 负责人: AbdelRaheem, Esam
• 金额: $ 0.87万
• 依托单位: University of Windsor
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2008
• 资助国家: 加拿大
• 起止时间: 2008-01-01 至 2009-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=395704
• 关键词: Design; VLSI; implementations; DSP; algorithms

The proposed research will leverage the invistigation of innovative solutions in the design and VLSI implementations of digital signal processing (DSP) algorithms for communication systems. Solutions that would lead to high performance, low complexity and low-power consumptions will be adopted. Objectives of the project are: (1) To further develop blind equalization techniques that have shorter time-to-convergence (TTC) quality to suit high-speed communication systems and for other  modulation schemes implemented in wireless communication standards (i.e., DPSK, DQPSK, GMSK, etc.). (2) To further develop computationally-efficient blind adaptive equalization techniques that reduce both the amount of computations and hence increase the system's throughput, and/or decrease hardware complexity. (3)To develop programmable/reconfigurable blind adaptive equalizer so that their filter lengths, adaptation parameters, and error measure are variables according to the modulation utilized in the receiver for multi-standard future communication equipments (also as in software-defined radios). (4) To develop low-lardware-complexity and/or computationally-efficient adaptive algorithms for echo cancellation applications in communication systems. (5)To achieve low-power in blind adaptive equalizers and adaptive echo cancellers (AECs) to respond to the increased demand of fast-growing mobile communication services. (6)To develop VLSI implementations of blind adaptive equalizers and echo cancellers that incorporate both high-speed, low-power, and low-complexity requirements. (7) To achieve performance enhancement and robustness of 802.11a/RA for high vehicular velocity, so that higher data rates may be achieved in a 5.9GHz Dedicated Short Range Communication (DSRC) system.   (8)To confirm feasibility, consider the complexity of the receiver design, and maintain consistency with the 802.11a/RA standard.

拟议的研究将利用invisigation的创新解决方案的设计和VLSI实现的数字信号处理（DSP）算法的通信系统。将采用高性能、低复杂性和低功耗的解决方案。该项目的目标是：（1）为了进一步开发具有较短的收敛时间（TTC）质量的盲均衡技术，以适应高速通信系统和用于在无线通信标准中实现的其他调制方案（即，DPSK、DQPSK、GMSK等）。(2)为了进一步开发计算效率高的盲自适应均衡技术，该技术既减少了计算量，又因此增加了系统的吞吐量，和/或降低了硬件复杂性。(3)To开发可编程/可重新配置的盲自适应均衡器，使得它们的滤波器长度、自适应参数和误差测量根据在用于多标准未来通信设备（也如在软件定义无线电中）的接收机中使用的调制而可变。(4)开发低硬件复杂度和/或计算效率高的自适应算法，用于通信系统中的回声消除应用。(5)To在盲自适应均衡器和自适应回波消除器（AEC）中实现低功率，以响应快速增长的移动的通信服务的增加的需求。(6)To开发盲自适应均衡器和回声消除器的VLSI实现，这些实现同时满足高速、低功耗和低复杂度的要求。(7)为了实现802.11a/RA在高车辆速度下的性能增强和鲁棒性，以便在5.9GHz专用短程通信（DSRC）系统中可以实现更高的数据速率。 （8）为了确认可行性，考虑接收机设计的复杂性，并保持与802.11a/RA标准的一致性。