Circuit-level analysis and design methodologies for nanoscale integrated systems

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With the rapid progress in semiconductor technology toward nano-scale electronics with smaller dimension and less power, the circuit designers of single-electron tunneling (SET) devices and circuits are facing two unique challenges: (a) efficient performance evaluation, and (b) advanced design methodology. The fast performance analysis is needed for large circuits where the existing simulation is computationally prohibitive, while the investigation of advanced design methodologies is required to deal with such special problems as reliability and adaptability with the technology. The primary goal of this proposal is to meet the above challenges. First, analysis of SET circuits is much difficult due to the stochastic nature of the tunneling events within the device and their strong correlation. We are going to tackle this issue by developing new models for both delay and power dissipation with SET networks. Secondly, we will look at design methodologies toward highly reliable and adaptive SET circuits. Reliability is a key issue because of random background charge (RBC) problem. Adaptability is important as SET circuits are designed typically in a bottom-up fashion. We will focus on the combination of SET technology and neural networks. Our circuit-level solution to the reliability problem is to use hardware redundancy. To address the adaptability problem, we will borrow some ideas from biological systems and implement certain learning algorithms in the neural networks. Finally, we will apply the proposed techniques to real circuits for image processing. In the long run, we are going to develop computer-aided design (CAD) tool support for SET circuit/system design. This will eventually lead to various applications (such as quantum computing, automotive electronics, and medical diagnosis systems) of SET or CMOS/SET hybrid integrated circuits, contributing to rapid growth of next-generation electronics industry nationwide in the foreseeable future.