Circuit-level analysis and design methodologies for nanoscale integrated systems

纳米级集成系统的电路级分析和设计方法

• 批准号: 249499-2006
• 负责人: Chen, Chunhong
• 金额: $ 1.46万
• 依托单位: University of Windsor
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2008
• 资助国家: 加拿大
• 起止时间: 2008-01-01 至 2009-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=394347
• 关键词: Circuit; level; analysis; design; methodologies

With the rapid progress in semiconductor technology toward nano-scale electronics with smaller dimension and less power, the circuit designers of single-electron tunneling (SET) devices and circuits are facing two unique challenges: (a) efficient performance evaluation, and (b) advanced design methodology. The fast performance analysis is needed for large circuits where the existing simulation is computationally prohibitive, while the investigation of advanced design methodologies is required to deal with such special problems as reliability and adaptability with the technology. The primary goal of this proposal is to meet the above challenges. First, analysis of SET circuits is much difficult due to the stochastic nature of the tunneling events within the device and their strong correlation. We are going to tackle this issue by developing new models for both delay and power dissipation with SET networks. Secondly, we will look at design methodologies toward highly reliable and adaptive SET circuits. Reliability is a key issue because of random background charge (RBC) problem. Adaptability is important as SET circuits are designed typically in a bottom-up fashion. We will focus on the combination of SET technology and neural networks. Our circuit-level solution to the reliability problem is to use hardware redundancy. To address the adaptability problem, we will borrow some ideas from biological systems and implement certain learning algorithms in the neural networks. Finally, we will apply the proposed techniques to real circuits for image processing. In the long run, we are going to develop computer-aided design (CAD) tool support for SET circuit/system design. This will eventually lead to various applications (such as quantum computing, automotive electronics, and medical diagnosis systems) of SET or CMOS/SET hybrid integrated circuits, contributing to rapid growth of next-generation electronics industry nationwide in the foreseeable future.

随着半导体技术向纳米尺度、小尺寸、低功耗方向发展，单电子隧穿（SET）器件和电路的设计者面临着两个独特的挑战：（a）有效的性能评估;（B）先进的设计方法。快速的性能分析是必要的大型电路，现有的模拟计算是禁止的，而先进的设计方法的调查是需要处理这样的特殊问题，如可靠性和适应性的技术。本提案的主要目标是应对上述挑战。首先，由于器件内隧穿事件的随机性及其强相关性，SET电路的分析非常困难。我们将通过开发SET网络的延迟和功耗的新模型来解决这个问题。其次，我们将着眼于高可靠性和自适应SET电路的设计方法。由于随机背景电荷（RBC）问题，可靠性是一个关键问题。由于SET电路通常以自底向上的方式设计，因此适应性很重要。我们将重点介绍SET技术和神经网络的结合。我们对可靠性问题的电路级解决方案是使用硬件冗余。为了解决适应性问题，我们将借鉴生物系统的一些思想，并在神经网络中实现某些学习算法。最后，我们将提出的技术应用到真实的电路的图像处理。长远来说，我们会发展计算机辅助设计（CAD）工具支援SET电路/系统设计。这将最终导致SET或CMOS/SET混合集成电路的各种应用（如量子计算，汽车电子和医疗诊断系统），有助于在可预见的未来在全国范围内快速增长的下一代电子产业。