Towards ultra-low power digital circuit design with single-electron tunneling technology

利用单电子隧道技术实现超低功耗数字电路设计

• 批准号: 249499-2012
• 负责人: Chen, Chunhong
• 金额: $ 1.31万
• 依托单位: University of Windsor
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=570627
• 关键词: Towards; ultra; low; power; digital

As today's electronic devices are pushed toward nanometer scale, single-electron tunneling technology (SET) plays an increasingly important role in reducing both power consumption and physical size of future electronic systems. In SET-based circuits, individual electrons can be transported in a controlled manner for both analog and digital signal processing. While the opportunities created by SET devices for technical breakthroughs in electronics are clear, circuit designers are facing a lot of practical design challenges ahead. This research proposal is an attempt to explore the approaches to analyzing and designing SET-based digital systems with improved performance (such as low power consumption, small delay and high reliability). Since electron transports within SET devices are stochastic in nature, new models are required to evaluate the power, delay and reliability in different ways. One of the unique characteristics with SET devices is the Coulomb blockade oscillation. This allows the designers to develop novel structures in order to achieve high-performance implementations. SET circuits are also subject to the background charge fluctuation, a serious deficiency which could entirely suppress the Coulomb blockade. Therefore, there is a strong demand for techniques at different design abstraction levels to increase the circuit's immunity against these noises. The proposed research work aims to (a) develop the modeling for power, delay and reliability with SET circuits, (b) adopt new architectures (such as feedback and hybrid CMOS-SET architectures) for cost-effective implementations of digital systems, and (c) address the SET background charge effect through a variety of methodologies, such as Boltzmann machines and redundancy strategies methods. The ultimate goal is to overcome the technical hurdles with SET technology for more practical applications in the post-CMOS era.

随着当今电子器件向纳米尺度发展，单电子隧穿技术（SET）在降低未来电子系统的功耗和物理尺寸方面发挥着越来越重要的作用。在基于SET的电路中，单个电子可以以受控方式传输，用于模拟和数字信号处理。虽然SET器件为电子技术突破创造的机会是显而易见的，但电路设计人员面临着许多实际的设计挑战。 本研究计画的目的在于探讨以SET为基础之数位系统的分析与设计方法，以改善系统的效能（如低功率消耗、小延迟与高可靠性）。由于SET器件内的电子输运本质上是随机的，因此需要新的模型来以不同的方式评估功率、延迟和可靠性。SET器件的独特特性之一是库仑阻塞振荡。这使得设计人员能够开发新的结构，以实现高性能的实现。SET电路也受到背景电荷波动的影响，这是一个严重的缺陷，可以完全抑制库仑阻塞。因此，有一个强烈的需求，在不同的设计抽象层次的技术，以增加电路的抗干扰能力，这些噪声。 本研究的目的是：（a）建立SET电路的功耗、延迟和可靠性模型;（B）采用新的结构（如反馈和混合CMOS-SET结构）以实现数字系统的低成本实现;（c）通过各种方法（如Boltzmann机和冗余策略方法）解决SET背景电荷效应。最终目标是克服SET技术的技术障碍，在后CMOS时代实现更实际的应用。