Towards ultra-low power digital circuit design with single-electron tunneling technology

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As today's electronic devices are pushed toward nanometer scale, single-electron tunneling technology (SET) plays an increasingly important role in reducing both power consumption and physical size of future electronic systems. In SET-based circuits, individual electrons can be transported in a controlled manner for both analog and digital signal processing. While the opportunities created by SET devices for technical breakthroughs in electronics are clear, circuit designers are facing a lot of practical design challenges ahead. This research proposal is an attempt to explore the approaches to analyzing and designing SET-based digital systems with improved performance (such as low power consumption, small delay and high reliability). Since electron transports within SET devices are stochastic in nature, new models are required to evaluate the power, delay and reliability in different ways. One of the unique characteristics with SET devices is the Coulomb blockade oscillation. This allows the designers to develop novel structures in order to achieve high-performance implementations. SET circuits are also subject to the background charge fluctuation, a serious deficiency which could entirely suppress the Coulomb blockade. Therefore, there is a strong demand for techniques at different design abstraction levels to increase the circuit's immunity against these noises. The proposed research work aims to (a) develop the modeling for power, delay and reliability with SET circuits, (b) adopt new architectures (such as feedback and hybrid CMOS-SET architectures) for cost-effective implementations of digital systems, and (c) address the SET background charge effect through a variety of methodologies, such as Boltzmann machines and redundancy strategies methods. The ultimate goal is to overcome the technical hurdles with SET technology for more practical applications in the post-CMOS era.