Architectures and circuits for high-performance highly integrated wireless/wireline communication systems

模拟、混合信号（包括模拟和数字子电路的设计）和射频（RF）构建模块通常是通信系统和微系统的性能瓶颈。这些模块通常决定系统的速度和/或功耗。本研究的目标是开发适合高性能高集成无线/有线通信系统以及微系统的电路设计技术和收发器架构。该研究的重点是在深亚微米体CMOS技术中实现的系统，并在高达几十GHz的频率范围内工作。大块CMOS技术已经成为高性能集成解决方案的有前途的低成本替代方案（与化合物半导体技术相反，如GaAs）。此外，CMOS技术提供了在同一芯片上集成模拟和数字电路的可能性，是混合信号微系统的合适候选者。然而，批量CMOS技术的进步主要是由数字世界驱动的，因此CMOS技术的数字性能指标的增长速度明显快于模拟、混合信号和射频电路中的相应措施。虽然模拟和数字元件都利用了由于技术缩放而提高的操作速度，但与数字元件不同，模拟电路更受噪声和精度要求的限制。因此，模拟、混合信号和射频电路的性能通常只能有条件地受益于技术缩放，甚至可能随着电源电压的降低而恶化。一般来说，CMOS实现系统的净效益是由于技术的扩展，即由于在更先进的CMOS技术中（重新）设计系统而导致的整体性能改善，这是系统架构和电路设计技术的强大功能。因此，本研究的目标是在先进的CMOS技术中为模拟、混合信号和射频构建模块开发新的CMOS友好电路设计技术。

Analog, mixed-signal (designs that include both analog and digital subcircuits), and radio-frequency (RF) building blocks are often the performance bottleneck of communication systems and microsystems. These blocks usually dictate the speed and/or power consumption of the system. The goal of this research is to develop circuit design techniques and transceiver architectures that are suited to high-performance highly integrated wireless/wireline communication systems as well as microsystems. The emphasis of the research is on the systems implemented in deep submicron bulk CMOS technologies and operating in the frequency ranges up to a few tens of GHz. Bulk CMOS technologies have emerged as promising low-cost alternative (as opposed to compound semiconductor technologies such as GaAs) for high-performance integrated solutions. In, addition CMOS technologies provide the possibility of integrating analog and digital circuitry on the same chip and are suitable candidates for mixed-signal microsystems. However, advances in bulk CMOS technologies are mainly driven by the digital world and therefore digital performance metrics of CMOS technologies have grown significantly faster than corresponding measures in analog, mixed-signal, and RF circuits. Although both analog and digital components take advantage of the higher speed of operation due to technology scaling, unlike their digital counterparts, analog circuits are more constrained by noise and accuracy requirements. Hence, the performance of analog, mixed-signal, and RF circuits often only conditionally benefits from technology scaling and can even deteriorate with the trend in decreasing supply voltages. In general, the net benefit of CMOS implementation of systems due to technology scaling, that is, the overall performance improvement due to (re-)designing systems in a more advanced CMOS technology, is a strong function of the system architecture and circuit design techniques. Therefore, it is the goal of this research to develop new CMOS-friendly circuit design techniques for analog, mixed-signal, and RF building blocks in advanced CMOS technologies.